( DAC'14 Item 6 ) ----------------------------------------------- [12/18/14]
Subject: ARM, Synopsys DesignWare, Mentor VIP, plus Cadence IP went missing?
SNPS AND ARM RULE!: Going into DAC'14, one major predictor of what the hot
hard IP was going to be there was Gartner's 2013 semiconductor IP data:
ARM Holdings Ltd: ############################## ($1,058.4 M) 43.2%
Synopsys DesignWare: ########## ($340.6 M) 13.9%
Imagination Tech/MIPS: ###### ($220.5 M) 9.0%
Cadence Denali: #### ($125.0 M) 5.1%
Silicon Image: ## ($49.0 M) 2.0%
Ceva: ## ($41.7 M) 1.7%
Sonics: # ($36.8 M) 1.5%
Rambus: # ($34.3 M) 1.4%
eMemory: # ($27.0 M) 1.1%
Vivante: # ($24.5 M) 1.0%
all others combined: ############## ($490.0 M) 20.0%
ARM and Aart kicked ass in hard IP -- both with Gartner and the users. No
news there. Actually it wasn't Aart who gave SNPS the big lead in IP -- it
was Aart's Co-CEO Chi-Foon Chan who had started up DesignWare 18 years ago
waaay back in 1996 that gave SNPS $340 M in 2013 -- but I digress...
WHO KNEW?: What intrigued me in this survey was how many engineers who had
said that VIP (vs. hard IP) was their first interest in IP -- plus how many
who had mentioned Mentor Questa Verification IP specifically.
 
Who knew VIP was big and that Wally had a good piece of it??! I didn't!
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OOPS!: An embarassing IP side story started 30 months ago at CDNLive'12,
when Lip-Bu Tan had announced that he appointed Martin Lund from Broadcom
to be his SVP for all CDNS IP.
"Lund's primary focus is to expand the Cadence design IP portfolio"
- Cadence press release (03/05/12)
What was embarrassing is two part: first, 2 years later Martin Lund skipped
the CDNLive'14 meeting -- and second, barely any engineers at DAC'14 had
mentioned Cadence IP whatsoever. Or said numerically: out of the 93 total
user comments here on IP only 3 were on Cadence IP -- and they were 2 minor
Denali Memory IP cites and one Verisity Specman "e" VIP cite. OUCH!!!
SURVEY QUESTION #2:
"What type of IP (hard/soft/VIP) INTERESTED you at DAC?
For what specific protocals/uPs/memories/standards?
What company made the IP you're interested in?"
VERIFICATION IP (VIP) COMMENTS:
Mentor's Questa VIP Library interested me.
It has the protocols we are currently using. ARM AMBA AXI, AHB,
APB, I2C and USB 2.0. I like that all of the VIP is written in
pure System Verilog, not proprietary code wrapped in SV. Lets
us use VCS and Incisive, too.
Does UVM functional coverage and protocol checking assertions.
Their bus drivers run in "active" or "passive" mode to sim blocks
in chip-level. Transactions can be viewed in the waveform views.
Easy debug.
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I am mainly interested in VIP. We mostly use Questa VIPs from
Mentor. PCIe, CPRI, MIPI, AMBA4 and memory DDR. Very happy with
them so far. Easy to plug in, OVM and UVM, and debug switches
in Questa. Configurable.
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We are giving the MENT VIP a serious look. Since we buy so much
DesignWare, we go out of our way to seek out non-Synopsys VIP to
check it. Using Synopsys VIP to check Synopsys IP is stupid.
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SNPS Designware + Questa VIPs
Go UVM!
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I like QVIP macros for connecting I/O signals to PCIe IP.
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Like Questa VIP - independent of DesignWare.
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ARM AMBA AXI4 parts and DW for HDMI
Questa VIP for AMBA AXI4 and HDMI
Questa LPDDR4 memory models
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Our local MENT Veloce sales rep says that Questa VIP is selling well.
He's so transparent.
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QVIP AMBA 5 CHI
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Our hard IP from Synopsys. Then VIP from Mentor to check it.
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Mentor Questa VIP and SmartDV VIP. They're a small Indian company.
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VIP: SmartDV VIP for MIP, PCIe, USB.
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Looked at VIP from SmartDV. Small start-up. First DAC.
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VIP: Avery Design for PCIe, NVMe, SOP/PQI, AHCI
We like to do business with Avery because we can talk directly
to their VIP R&D. Compliance, protocol checking, BFMs, Agents,
Transactors, Monitors. Complete deal.
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Mostly Synopsys DesignWare VIP from our bundled deal.
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DW Discovery VIP for all ARM parts.
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Looking for non-Synopsys VIP for DW HDMI 2.0 RX
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CDNS Verisity Specman "e" VIP for AMBA 5 CHI. Our guys like "e".
It's good to see Lip-Bu still supporting it.
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HARD IP COMMENTS:
We use DW Building Block IP every day.
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DesignWare Foundation
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Do you mean Designware Building Block IP?
It comes with every Design Compiler license.
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DW Adders, MACs, ALUs
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Are Synopsys DW Building Blocks IP "hard" or "soft" IPs?
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DesignWare
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DW Building Block IP
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Designware?
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We use DesignWare Foundation.
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Does DW Building Block IP count?
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DW_fp_addsub, DW_fp_mac, DW_fp_sincos, DW_fp_sub, DW_fp_i2flt,
DW_fp_flt2i, DW_fir, DW_iir_dc, DW_fifoctl_2c_df
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Hard: DW Building Block IP
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Hard: DW AMBA 4 AXI, USB, HDMI, LDDR4
VIP: DW AMBA 4 AXI, USB, HDMI, LDDR4
Not sure how wise that is.
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We use DW every time we use DC.
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DW HDMI 2.0 RX
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DW
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Are you asking about which DW blocks we use?
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Want NVM IP. Synopsys DW Aeon, Kilopass, Sidense.
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We were looking for anything HDCP 2.2.
Synopsys and others say they have it.
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I dunno.
Denali and Synopsys both have pretty good IP stories here.
No real opinions.
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The 2 big guys, Synopsys DesignWare and Cadence Denali.
The DesignWare guys FINALLLY got their act together by delivering a
complete solution, i.e. control + phy IP.
In the past, it has been crazy; SNPS phy team did not talk to the
SNPS control team.
Also, we still have gaps in verification of the 3rd party hard IP.
At the SOC level, we still don't know if the hard IP 100% meets the
intent after integration?
VERY tough problem to verify unless you 100% verify ALL use models
This is a ton of work. It is not copy and paste then done.
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I visited Cadence there and their IP offering looks good.
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CAST H.264 video IP, CAST MPEG Transport Stream IP
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Arasan MIPI CPHY-DPHY -
4 channel D-PHY does 4K video at 30 fps, 1080p at 120 fps.
3 channel C-PHY does 4K video at 60 fps, 1080p at 240 fps.
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Arasan UFS & USB IP
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We liked InnoSilicon for high speed interfaces such as USB3.0,
MIPI, HDMI, etc.
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InnoSilicon PHY
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SmartDV LPDDR3 Memory Models
SmartDV I2S Master Controller
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Are memory compiler "hard" or "soft" IP?
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Memoir Systems.
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Biggest lie: Memoir was looking for embedded memory customers.
Apparently they were looking to get bought by Cisco.
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Considering eSilicon TCAM Mem Compiler for 16FF
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eSilicon for hard memory IP.
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We use TCI for our clock generator PLL's.
Does TSMC CL025G 800 Mhz to TSMC CLN16FF+ 3.5 Ghz
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True Circuits Inc. and Silab Tech for low jitter PLLs.
TCI is established. Silab has new PLL Autogen tool.
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PROCESSOR CORE IP COMMENTS:
We design everything around ARM cores here.
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8-core ARM Cortex-A53 system to run 64-bit Linux
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Saw TSMC's 16 nm ARM Cortex-A57 and Cortex-A53 tape-out.
Good presentation.
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ARM
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We're an ARM house.
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All things involving possible holes inside the ARM Trustzone get
our immediate attention.
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ARM 64-bit everything
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We went to this DAC to discuss how to best cut both ARM dynamic
and leakage power inside Encounter.
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Cortex-A53
Our SW guys are all busy porting 32-bit intructions into A64.
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Mail T628/78 GPU
(Well, we do do graphics.)
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Anything ARM and IP-XACT is a joke. Socrates doesn't work.
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BIGGEST LIE:
IPXACT will increase your productivity. It does NOT!
It is a perfect interchange format which all "writes" and all
"readers" speaks the same language and dialect. It does NOT!
Cannot even agree on "leading zero", CRAZY!
Very long ways to go to exchange meta data between Tool A to
Tool B or View A to View B
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University does Cortex-MO inside Xilinx Vivado was interesting.
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Do you know who's using the ARM Embedded Memory Compiler?
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We're old Artisan users. Not exactly IP, but ARM sells it.
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Odd. No Simon Segars at DAC this year.
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Everything is ARM for us. No MIPS.
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Story tip -- Hossein Yassaie, CEO of Imagination Tech, does the
DAC IP keynote at DAC'14, yet has no MIPS exhibit booth? Weird.
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When I asked the ARM Pavillion guys where the MIPS booth was,
they frowned at me.
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DesignWare ARC Cores. 32-bit works well for our applications.
Also we get an DW ARC 770D at better price than for ARM Cortex-A12.
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DW ARC 770D - our chip will use Linux
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Synopsys Virage ARC AS211SFX and AS221BD Audio
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Do you know anyone who's sucessfully taped out a production chip
with any CAST BA2x 32-bit processor core in it?
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NETWORK-ON-CHIP (NOC) COMMENTS:
Hard IP: Sonics SGN or Ateris FlexNoc
Leaning Sonics because they still have R&D.
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Curious if/how Janac rebuilt.
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SGN and CoreLink
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Sonics
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Came to DAC to figure out AMBA 3, AMBA 4, AMBA 5, CHI, AXI,
AHB, APB, and the 6 CoreLinks ARM has.
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We're designing to Cortex-M7's. Choosing CoreLink or SGN.
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Entertaining to watch the Sonics people and the Arteris people
pretend the other company didn't exist in the ARM pavillion.
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FPGA IP COMMENTS:
I saw an embedded FPGA IP developed by AdicSys that seems quite
interesting.
The founders are ex-M2000 and they've distributed soft FPGA IP
that's completely integrated into a standard ASIC flow.
Is AdicSys another fail or a first successful FPGA IP company ???
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Not sure what to do with it but the embedded FPGA IP from Menta
is intriguing. Menta is a stupid name, though. These guys hadn't
thought out that maybe Menta and Mentor might get confused?
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"OTHER" IP COMMENTS:
We're interested in peripheral IPs both in hard/soft IP and VIP.
We will have these interfaces in our chip and want to know the
availability and vendors who have them.
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We want IP for countermeasures to physical attacks.
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UPF 2.1 Want tools to support it ASAP. Tired of converting.
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Most of the IP I have been looking for is pre-standard. I would
be curious to know peoples thoughts on how to make a market for
pre-standard IP/VIP.
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Not so focused on IP this time at DAC.
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I asked Mike Giafagna why he had left Atrenta for eSilicon.
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Ernie Brickell's Intel Security keynote was fascinating!
Too bad it was on DAC Thursday.
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