( DAC'15 Item 8 ) ----------------------------------------------- [12/18/15]
Subject: Real Intent, OneSpin, Indago and the Atrenta-SNPS buyout concerns
CHAOS IS OPPORTUNITY: Exactly as I predicted 35 days *before* it happened,
on the first day of DAC, Aart announced he bought Atrenta for an undisclosed
sum -- which caused a sudden panicked tire-kicking shopping spree for all
those Atrenta SpyGlass and BugScope users.
No, customers are NOT bailing on Atrenta -- they're just concerned and they
used DAC as a place to find out what viable alternatives (like Real Intent,
OneSpin 360, Cadence Indago, Mentor QVM) they have if SNPS messes up Atrenta
in either tech support or pricing terms.
As for Atrenta BugScope, my spies report that Yunshan Zhu has NOT stayed on
at Synopsys Atrenta. Bad news for NextOp users. Yunshan was the founder
of NextOp -- which created BugScope. This means totally new people are now
doing the tech support and R&D on BugScope. Not good for BugScope users.
And one weird thing -- after Cadence paid a whopping $146 M in net cash to
acquire Kathryn Kranen's JasperGold tool last year, not a single user at
this DAC'15 mentioned Jasper at all this year...
SURVEY QUESTION #1:
"What were the 3 or 4 most INTERESTING specific EDA tools
you saw at DAC this year? WHY did they interest you?"
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With Atrenta in play, we're looking harder at Real Intent and Indago.
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Real Intent to possibly replace SpyGlass, depending on what Aart
does.
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If Atrenta prices go down (which we seriously doubt), we buy more
SpyGlass.
If Atrenta prices go up (which we expect), looking at Real Intent.
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Don't know. Real Intent might replace SpyGlass for us.
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In Ascent vs. SpyGlass eval right now.
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Biggest Lie?
"Your SpyGlass customer support won't change as a result
of the SNPS acquisition."
They actually said that to me with a straight face.
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Upside: We will now get SpyGlass and BugScope almost free as
part of our package license buy from Synopsys.
Downside: Even though we're not a Tier 1 account, Atrenta customer
support would treat us like kings whenever we had any
issue. Now because we're nobodies, we'll get the standard
wait-in-line Synopsys customer support that all the other
nobodies get -- but now for SpyGlass and BugScope, too.
- Atrenta user on the DAC floor (06/08/15)
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Real Intent
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Once our 3 year deal runs out, we'll be shopping heavily at Real Intent
and any other small start-up that competes in verification. Our MGMT
believes that our verification tools should come from a different
vendor than our development tools; otherwise it's asking a fox to
guard the chickens.
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Wanted to check whether we could identify design bugs with Real Intent
that were being missed before.
Started with Ascent-Lint on one of our small a8051 microcontroller IP
blocks which was in pure Verilog design and 17K gates in size.
From the start, we noticed that Ascent Lint was very easy to run.
Within minutes getting it installed we were able to run the tool on
our a8051 with practically no time spent on set up.
We caught a few issues even on it. One FSM was missing a "default"
statement. The designer missed this issue because of an involved mix
of pragmas and `defines in the RTL code. Ascent Lint ran in under a
minute to find the need to make a RTL fix for this. There were few
other minor FSM-related issues identified we passed those on to the
a8051 design team.
Next we ran their Meridian CDC clock-domain analysis tool on our
Ethernet MAC IP, a 40K gate Verilog design which had 4 different
clock domains.
The first phase to running Meridian CDC is setting up the environment
so the clock definitions and resets are identified correctly. It
reads our existing SDC constraints and our RTL code to automatically
create its environment setup. The tool created missing "reset" related
information automatically. We reviewed the environment file and no
manual editing was required from our side.
When running Meridian to catch CDC problems, it was correctly able to
identify our CNTL synchronizer and our other synchronizer structures
automatically. The analysis report can be debugged using the Synopsys
Verdi environment. We liked the color coding of clock domains in the
RTL source and in the generated schematic of the synchronizer logic.
The Meridian reports provided appropriate details of the violations
without bombarding us with too much information. We noticed "reset"
domains were not color coded. (We were told this feature was already
planned in the next version of Meridian.)
After the end of our eval, we decided to start using both Real Intent
tools on our next IP development project. We also plan to recommend
Ascent Lint and Meridian CDC tools to our consulting clients.
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Real Intent was one of the most interesting because we use their tools
already and wanted to know what new stuff they had coming up. Indeed,
they have expanded their product portfolio and made some improvements,
which helps our design flow.
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FYI -- Yunshan is leaving Atrenta. He's not going on to SNPS.
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I wouldn't call it a lie, but I'm not clear on why both Atrenta and
Real Intent were tagged as doing "Silicon Virtual Prototype".
Seems like a stretch.
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1. The Vtool company demonstrated a great log analyzer. You can view
your log in waveforms, do some filtering... I liked the design of
the tool, with user experience in mind.
I liked the concept of the open Debug Data API jointly announced at
DAC by Mentor & Cadence. FSDB being owned by SNPS, their common
competitor, this is how they strike back.
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1. OneSpin mentioned a new product they were working on (no name given)
for automating formal proofs of fault behavior. We've used formal
tools in the past to examine fault conditions, but we had to insert
the fault models ourselves at the gate level.
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Verifyter Pindown: besides finding which commit broke your daily/weekly
regression, they collect statistics about the
characteristics of commits that break things.
Cadence Indago: was announced at DAC. We have been using some of
the components for year now, so I do not know if
it counts. Really helps debugging.
Onespin: has a tool to put properties in C code. Could be
used test equivalency.
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The OneSpin tools
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Internally, we use the Questa simulator and the Questa Verification
Management (QVM) tool for our IP Core verification and regression testing.
We use QVM to manage the functional verification of our IP cores. It lets
us create comprehensive verification plans and track our verification
results versus that plan. This includes tracking a wide range of
System Verilog covergroups with coverpoints and cross coverage, plus
managing hundreds of verification simulation runs and their contribution
to the final results. We like how QVM can report the results back to
our original verification plan.
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Related Articles
Atrenta SpyGlass CDC and BugScope, plus CDNS JasperGold vs. IFV
NextOp says dynamic analysis is how assertion synthesis works
JasperGold Apps, Vennsa OnPoint, NextOp BugScope were #5 at DAC
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