( DAC 99 Item 5 ) ----------------------------------------------- [6/25/99]
WE'RE ALL GOING TO THE PROMISED LAND! (YET AGAIN) Christianity talks
about getting into Heaven; Islam focuses on Paradise; Buddism and Hinduism
offer an ultimate reincarnation into blissful Nirvana -- every major world
religion offers its followers entrance into some sort of 'Promised Land'.
This year's DAC was no different in offering the promise of C/C++ based
design as being the ultimate chip/software/system designer's ticket into
personal ecstasy. The basic idea is that in the near future, simulation,
synthesis, timing, and even your system's software will all be written
in C/C++ with happily blurred lines between what part of your design is
ASIC and what part is microprocessor(s) running software. And, Oh! What
a blissful state that will be!
To make the first converts, some start-ups offer C/C++ to Verilog/VHDL
translators like C-Level Design ( http://www.cleveldesign.com ), CynApps
( http://www.cynapps.com ), and Frontier ( http://www.frontierd.com ).
And there's already a company, LavaLogic ( http://www.lavalogic.com )
that's offering the heretical idea of translating *Java* to synthesizable
Verilog. These tools all effectively give designers the basic ability to
create C/C++/Java -> translate 2 Verilog/VHDL -> Design Compiler to gates.
(Not to be left behind, Synopsys in their NDA suites, discussed 'Scenery',
a way to standardize C/C++ for synthesis purposes and their C-based
synthesis tool -- which is almost identical to CynApps' Cynlib approach.)
"Try using the C/C++ EDA tools, and you will quickly see what they can
and cannot do. The company I work for has used high-level synthesis
tools for a long time. So far, no C/C++ tools can provide what we
need. But then again, we are tough customers."
- Geir Hedemark, Univ. of Oslo, Norway
"I agree with Geir. Evaluate some of the tools and you will quickly
see how restricted you are and the things you cannot model. Stick
with behavioral Verilog or VHDL and the world will be a better place.
The observation that one engineer had around here when discussing the
C/C++ vs. HDL argument was that the more you restrict C++ by using
class templates, etc., the more you shave off the language so that
you can synthesize it, the more funky crap you add into the language
to simulate concurrency already found in HDLs, your 'language'
approaches Verilog/VHDL! So, just stick with an HDL and be done
with it."
- John Reynolds of Intel
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