( DVcon 04 Item 11 ) --------------------------------------------- [ 05/26/04 ]
Subject: Cadence Palladium, Verisity Axis, Mentor IKOS & Celaro, EVE, Tharas
HOME COOKING When it comes to emulators/accelerators, most (52%) designers
either stay away or (20%) use FPGAs to build their own homebrew solutions.
"Does your company use HW emulators/accelerators like Cadence
Quickturn Palladium, Mentor IKOS/Meta Systems, Verisity Axis,
Tharas, Pittsburgh Simulations, EVE, or Aptix?"
don't use : ########################## 52%
homebrew with FPGAs : ########## 20%
Cadence Palladium : ###### 11%
Verisity Axis : #### 7%
Mentor IKOS : ## 3%
Mentor Celaro : # 2%
EVE : # 2%
Tharas Hammer : # 2%
Aptix : ## 4%
Alatek : # 1%
Pittsburgh Sim : 0%
But those who like off the rack clothing generally prefer Cadence Palladium
as their emulator of choice. Subtracting out all 72% of the "don't use" and
"homebrew FPGA" people leaves only the commercial emulators:
Cadence Palladium : ####################################### 39%
Verisity Axis : ######################## 24%
Mentor IKOS : ########### 11%
Mentor Celaro : ###### 5%
EVE : ###### 5%
Tharas Hammer : ###### 5%
Aptix : ############# 13%
Alatek : ### 3%
Pittsburgh Sim : 0%
In the recent ESNUG 428 #1, a cocky Palladium smacks around Axis in a
user's comparitive emulator benchmark. Looks like the Verisity folk have
some work to do to fix up their new Axis aquisition...
We try to avoid emulation whenever possible, the investment (man-power
to set-up and support the emulation environment and gear itself) makes
it a choice of last resort. Hardware protoyping using FPGAs in-system
has given us better pay-back -- and the code that's written IS the
system code we need anyway.
- Tom Heynemann of Hewlett-Packard
We do not use HW emulators/accelerators.
- Samuel Russell of Ceva, Inc.
No, we develop our own FPGA based platforms.
- Yuval Itkin of Metalink Broadband, Ltd.
Planning on using either Palladium or a home-grown National Instruments
FPGA set-up in current project.
- Fraser Dallas of Motorola GSG (Scotland)
We have used Axis HW mainly in the targetless emalation mode, will move
to ICE (in-circuit emulation) to run real application. Evaluated the
EVE product and found it's not good at large custom design with
complex gated clocks.
The man power requirement is 1.5 full time cad guys on flow developement
and support and one part time verification engineer for debugging. For
the emulation resource, in the first bring up phase, we need to have
1.5 cad, 2 verification, 1 OS and 1 application guys for 6-8 weeks to
boot the MP (multi-processor) Linux.
- [ An Anon Engineer ]
Palladium. We regress on Palladium instead of workstations. The setup
depends on the mode used and the size of the design -- no more than
a 1-2 weeks.
- Carl Harvey of Cirrus Logic
We use Cadence Palladium's ICE (In-Circuit Emulation). Since last year,
Palladium machines are the baseline of our verification process for up
to 3 Millions gates SoC, excluding RAMs and ROMs. It compiles faster
compared to the old FPGA-based Quickturn Mercury --- e.g. 40 minutes
instead of 8 hours. A typical compilation requires a single SUN Blade
2000 workstation. We avoid all timing issues related to FPGA mapping as
well as partitioning steps. I/O timings are thus well-maintained
between compiles. We enhance our debug performance by full vision upload
(we can upload waveforms, and still probe in-circuit signals without
recompilation) and embedded synthesizable memory (SDRAM and DDR) models,
avoiding external modules and additional logic to slow down these
external modules speed.
The main design issue we currently run into is we can't use their 1x
mode. It requires a software upgrade from Cadence that's not currently
available. We use their 2x mode by default, which decreases run time
performance by 1/2. We cannot yet assess the impact on capacity for a
1x mode till we get it. Our first acceleration trials on Palladium were
not very encouraging since legacy and non-synthesizable testbenches can't
be embedded on the complete system. Furthermore, we have encountered
issues with the HDL-i synthesizer used for acceleration purposes (instead
of PKS BuildGates used for physical synthesis). We've been unsuccessful
in running Formal proof between various generated netlists.
Overall, Palladium's ICE is a key tool of our verification process and
low level driver development. It's now well integrated in our design
flow and we use it heavily -- 24 hours per day over 7 days. We plan to
continue using Palladium for larger SoC verification assuming its run
time performance is improved.
- Patrick Rousseau of Philips
EVE & Mentor IKOS.
Needed for realistic system level verification.
All depend upon people following design rules restrictions.
EVE - 1-2 days setup.
IKOS - 2-3 weeks setup.
- Winston Worrell of Microsoft
We have used them (I think IKOS and Aptix) and had a lot of trouble with
them. I haven't worked with them myself.
- Aviva Starkman of Northrop Grumman
Some colleagues use Axis (video sim).
- Stefan Rohrer of Micronas GmbH
Axis is top top top top of the line. I have tried in my past experience
Quickturn, Celaro (Meta System), and Palladium (the new generation).
- Remi Francard of STmicroelectronics
No
- Greg Arena of Intel Corp.
No. They are a huge resource drain, and provide useful data only
shortly before tape-out.
- Dan Steinberg of Integrated Device Technology
We use Altera prototype boards for HW-acceleration of block verification.
By adding the DUT as a co-processor to a NIOS-based platform in their
SOPC-builder and downloading the design over the LAN to the board, we
can run the block verification at-speed, use standard C tools to write
the test benches and do complex block verification dirt cheap.
- Joachim Strombergson of InformAsic AB
We've used Axis in the past and really like their boxes. Very easy
setup time; you can begin productive work very quickly. They also have
a great team of support engineers, quickly finding solutions for
problems.
It'll be interesting to see what becomes of Axis now that they're part
of Verisity. Axis has been a supporter of System Verilog. But many of
the testbench features in System Verilog directly compete with "e".
Do the Axis folks keep supporting accelerated testbench constructs
in System Verilog? On the other hand, Verisity had started their
"eCelerator" program, targeting any accelarator, etc... Do the Versity
folks continue this strategy, or instead focus on their now internal
boxes? Interesting times for Verisity...
- Mark Curry of Texas Instruments
None. We have a methodology of doing our own custom emulation with
multiple FPGAs.
- Alex Chao of Topspin Communications
We did. Not any more. Dropped maintenance on our IKOS box 4 years ago
and just dropped them on our Synopsys LMG boxes. ModelTech on a 2.5 Gig
Linux box runs faster than the emulator does.
- [ An Anon Engineer ]
We did our own FPGA board.
- [ An Anon Engineer ]
No. Too expensive. I'd rather buy more Sun workstations.
We do our own FPGA prototypes instead of HW acceleration.
- Terry Doherty of Emulex Corporation
Verisity Axis, Cadence Palladium, Aptix and Mentor Celaro
- Benoit Clement of STMicroelectronics
We currently do not use these kind of systems. We consider the threshold
too high to start using them: high costs, steep learning, unknown
reliability.
- Willem Sloof of Philips Microdisplay Systems
No, too expensive and too much work.
- Brad Hollister of NetSilicon, Inc.
We still use our Quickturn Mercury Plus box. We emulated a very complex
multi-clock M+ gate chip in Quickturn with good results. Since we are
now experienced at it, it doesn't take us more than 1 week or so to set
up a new design that fits easily in the box. If the design does not fit,
it can take a lot longer to shove in the gates.
- [ An Anon Engineer ]
We use our home-built emulation. Quickturn is too slow, too expensive,
and you can't get enough systems. IKOS is too expensive, not enough
systems. Have found it just a lot easier and cheaper to build our own.
You also can get enough of them in the hands of the FW people who really
add the value to doing emulation in the first place. Emulation simply
to make sure the hardware is good doesn't make sense. When it gives FW
a headstart, you really get the benefit.
- [ An Anon Engineer ]
In general I put this in the category of infinite monkies. If you try
to cover every possibility instead of intelligently directing your tests
then you need a large number of accelerators.
- Doug Hester of Chip World Consulting
Hardware emulators are like topless bars in Fallujah, Iraq. They are a
dying breed because of the outstanding innovations that EDA companies
have made. I have been involved with ASIC design teams that utilized
co-verification, and we did an outstanding job of analyzing bugs before
they ever made it to the lab. In fact, the only debugging we did in the
lab was board level debug, i.e., incorrect/faulty components, signal
integrity issues, etc.
- Simon Ramirez of Synchronous Design, Inc.
We have considered looking at emulators/accelerators, but our general
experience is that they are costly to buy, and very difficult to get good
results from. We currently prefer to invest in FPGA based testing, and
fast machines for simulation. This approach seems to be suitable for the
projects we are running at the moment.
- [ An Anon Engineer ]
We have an Alatek (large FPGA based) accelerator and have been evaluating
EVE. We are simulating large Xilinx and Altera FPGAs with Modelsim. We
like that these tools integrate with Modelsim allowing us to use the same
simulator and tests as our software only simulations. Performance is
about 12x-25x depending on how much of the simulation will run in the
accelerator. However, this is partLy because the Xilinx VHDL libraries
are very slow and we hand instantiate a few key parts of the designs.
The biggest problem is setup time and getting the accelerated simulation
to match the software simulations. This has really cut into the
effective use of these tools. When we were doing ASIC and had a
Quickturn box, we had a full time person pretty much dedicated to
bringing up a design in the Qucikturn. We can't justify that for FPGA
verification. Another issue is where a software simulator purchase lasts
for many years (under maintenance) you pretty much have to scrap your
hardware accelerator every 2-3 years.
- [ An Anon Engineer ]
Not currently using accelerators. Experimenting with a Xilinx based
accelerator for Matlab Simulink.
- Mike Murphy of Syracuse Research Corp.
Not in our department. We do FPGA prototyping on our development boards.
- Thomas Langschwert of Infineon
I sometimes uses Mentor Graphics Celaro Hardware box. It allows us to
run very long application benchmarks. Even without any experience,
beginners can quickly use it. I am not doing the setup part so I can't
talk about it.
- [ An Anon Engineer ]
Turnaround is too slow.
- Ram Sunder of Specular Networks
NO.
- Tomoo Taguchi of Hewlett-Packard
Nope, in the past I was in a company that used QuickTurn -- waste of $
and time. I think that these tool are good for mega companies like
Intel/Motorola/Sony ... not for under 1,000 eng companies.
- [ An Anon Engineer ]
Don't use them. We try to stay as much as possible on the instruction
set level and C. In the past we have used Zycad. Gate level was very
fast, but translation of the circuit and transformation of the stimuli
were always quite slow. In my opinion the costs of these accelerators
too high for the performance they are offering.
- Premysl Vaclavik of On Demand GmbH
We are evaluating a Cadence Palladium PD2. Preliminary indications are
that it will significantly improve our simulation throughput.
- [ An Anon Engineer ]
Considering EVE.
- Shivi Sidhu of Crimson Microsystems
Axis. Big set up time and only useable when the design is stable for
application based validation, rather than design verification.
Tendancy to cause avoidance of design for verification and become a
resource bottleneck in such projects.
- [ An Anon Engineer ]
No HW emulator/accelerator use. Unless you count the use of FPGAs.
- Tim Davis of Aspen Logic
No, we use the actual target hardware instead. Nice thing about FPGAs.
- Ray Andraka of Andraka Consulting
Too expensive, too much time needed to keep them running. Don't use 'em.
- Jonathan Craft of McData Corp.
Aptix. Very useful for us. We have one guy (out of 50) that does
nothing but Aptix and another that works on it part-time.
- [ An Anon Engineer ]
We use Aptix. Steep learning curve, but paid off in the long run. We
are considering purchasing ProDesign for future projects.
- Tim Ma of Mykotronx
No. We did in the past but found them too expensive. We've gone the
route of many fast Linux boxes to simulate with. We can't do a single
simulation as fast, but we can do many simulations quicker. Also, this
solution allows all engineers to simulate, not just one or two. We
also had a problem with libraries. (We used the old IKOS Insim
boxes). Our foundry stopped supporting these at the 130 or 180 nm
node. Management has been very reluctant to buy another costly hardware
platform that has a limited life.
- Maynard Hammond of Scientific Atlanta
We talked with Aptix in the beginning of the program gave them some
specifications/requirements and even a P.O. Our P.O. was returned within
in few days indicating Aptix will not be able to meet the requirements
due to complexity of our design in terms of # of gates, # of I/Os,
multiple power and clocks requirements. Looked at an accelerator as
well, but the accelerator cost alone was more than all our other tools
put together at that time. Decided to develop our own emulator. Glad
we made that decision. Otherwise it would have been very costly.
- Inder Singh of iVivity, Inc.
We are using Mentor IKOS, the setup time is very extensive. The folks
at Mentor we able to help us setup for a fee and the speeds are not as
much as they promised but it is about faster than what we were having
with just VCS.
- Subbu Muddappa of Woodside Networks
Investigating, but not using.
- [ An Anon Engineer ]
The only real experiences I have are for Verisity-Axis, which we use at
our site for a couple of years already. I like their approach where you
have a nice flow starting from acceleration (co-simulation), can go to
targetless emulation, and also to In-Circuit-Emulation, with the same
database, if you like.
If we start acclerating the NC-Sim simulation, the set-up time is
normally 2 weeks until we have an acceleration of 40X over just running
NC-Sim alone. This is dependent on design size, testbench activity
(running in software), etc. You can than improve your testbench by
making use of HW clock generation, 'HW assertions' etc. You can always
switch between software and hardware mode, so that you get a good idea
of the acceleration ratio achieved.
Debugging is good with their VCD on-demand technology that gives you
full visibility of signals even of a long Axis simulation.
- [ An Anon Engineer ]
One division uses Verisity Axis emulator. They serve their purpose for
simulation acceleration and system-level verification. They take 3
months to get working. The Axis emulator has better price-performance
then others and better debugging capabilities. But Verisity ownership
will probably screw up the price/performance advantage.
- [ An Anon Engineer ]
Do not use.
- [ An Anon Engineer ]
Don't use emulators/accelerators although we're starting to think about
it. We're currently synthesizing a subset of the ASIC to an FPGA
for prototyping.
- [ An Anon Engineer ]
Not yet but it should come soon.
- Laurent Claudel of Wavecom
They are used, but not on my site.
- [ An Anon Engineer ]
We do not use it. We use FPGA boards we design. These machines are
very expensive and take too much time to ramp up your project on.
- Boaz Ben-Nun of Starcore DSP
No, we don't use them,
- Gao Peng of Tongji University, China
NO
- [ An Anon Engineer ]
No - it's much cheaper to go to AlienWare and buy overclocked PCs,
install Linux, and run simulations on them. If that's still not fast
enough, then buy more of them. HW accellerators cost a fortune, and
are quickly obsolete. Design your test-suite so it can be run
in parallel.
- [ An Anon Engineer ]
Used Aptix in the past. These days, we go straight to G/P FPGA boards.
I think most of these systems (except maybe EVE Zebu) are just way too
expensive for the level of benefit they provide.
- Michiel Vandenbroek of China Core Technology Ltd.
Used Axis accelerators for last three years. Good tool. Three weeks
setup time should be enough.
- Chandresh Patel of Ciena Corp.
No accelerators used.
- [ An Anon Engineer ]
Yes, Palladium. Good and no other choice.
- Fred Liao of S3 Graphics
We use Palladium. We would not tapeout with them. We run thousands
of real tests on it. It's very useful to catch RTL bugs and SW driver
bugs. Worth the money. Just wish they were cheaper by 50%. After
the initial setup time, the emulation boxes run reliably except for
the occasional system bug due to FPGA card malfunctions.
- [ An Anon Engineer ]
Not yet, but also under consideration. It only make sense if we
do co-simulation which require more performance for simulation.
- Hsing Hsieh of Hitachi
We are evaluating Palladium although it is too expensive for a startup.
EVE is an option we are considering, although they lack the bridges
needed. FPGA prototyping is still first on our list.
- Sandro Pintz of Precision IO, Inc.
No. We just find the biggest FPGA in existence, stick it on a custom
PCB and fire up Synplicty.
- Mark Andrews of EFI, Inc.
We use Palladium and it has been a life saver. It has found many bugs
that we would have missed by allowing us to run very, very long
simulations. I don't like the fact that you can't do X-state
gate-level simulations. Everything seems to get initialized to 0, so
we still need to run gate-level to find initialization problems.
- Jerry Roletter of ATI
We used Axis. Did OK on first version of chip, to do the next chip it
would have taken a $200K upgrade. Ditched it and went with lots of
NC-Verilogs.
- [ An Anon Engineer ]
Tharas. Works out OK for gate sims and long RTL sims.
- [ An Anon Engineer ]
Axis was too expensive for us to consider. We evaluated Tharas about
2-3 years ago, two people spent over two months in our office and could
not get our RTL code running on their system. Recently we ended up
getting a Linux computing cluster set up running Carbon Design
software-based simulation. It requires a lot of support, but is getting
very impressive results, and our software team uses it for multichip
simulation and software development. We have not yet used Carbon for
much pre-silicon validation.
- Nathan Dohm of StarGen, Inc.
We are evaluating IKOS and Tharas.
- Sachin Mohan of Cypress Semiconductor
No. Too expensive.
- Don Monroe of Enterasys Networks
We have our own emulation team and we are happy with that. The same
team develops our own emulators/boards for real chip.
- Jithendra Madala of QuickSilver Technology
Just starting to use Mentor/IKOS Vstation. I'm hoping the extra time
needed to compile RTL for the emulator and the investment in the PC
Farm to do so will be worthwhile.
- Greg Schmidt of General Dynamics
None. Too costly/time-intensive for not enough payback. Just buy
faster servers and more sim licenses for the money you would spend.
plus our chips usually are too big for them to fit in anything
reasonable.
- [ An Anon Engineer ]
We do not use HW accelerators per se. We do use FPGA's to emulate
some designs, however. Our chip scales do not mandate emulators at
this time.
- Jim Lear of Legerity
No.
- Reza Shirali of Orbital Sciences Corp.
My impression of the HW emulators is that they take a specialized group
to run. They are very expensive and are therefore out of our realm.
- Bill Dittenhofer of Starkey
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