( DVcon 05 Item 2 ) --------------------------------------------- [ 10/25/05 ]
Subject: Cadence NC-Sim, Synopsys VCS, Mentor ModelSim, Aldec
CADENCE & SYNOPSYS TIE -- Remember that mindshare is not a zero sum game.
Just because X goes up, it does not necessarily mean Y must go down. It all
depends on what the users individually do. Here are the 2004 and 2005 stats
for Verilog and VHDL simulator use:
2004 - "Whose Verilog or VHDL simulator(s) do you currenty use?"
Cadence NC-SIM : ###################### 22%
NC-Verilog : ####################### 23%
Verilog-XL : ##### 5%
NC-VHDL : # 1%
Synopsys VCS : ################################## 34%
Mentor Modeltech : ######################################### 41%
Aldec : ####### 7%
Icarus : # 1%
Veriwell : # 1%
SimuCAD Silos-III : # 1%
SynaptiCAD : # 1%
2005 - "Whose Verilog or VHDL simulator(s) do you currenty use?"
Cadence NC-Sim : ########################### 27%
NC-Verilog : ##################### 21%
Verilog-XL : ## 2%
NC-VHDL : # 1%
Synopsys VCS : ########################################### 43%
VCS-MX : #### 4%
Mentor ModelSim : ################################### 35%
Aldec : ### 3%
Icarus : .5%
Veriwell : .5%
SimuCAD Silos-III : .5%
Finsim : .5%
For 2005, Cadence leads with 27% + 21% + 2% + 1% = 51% total Verilog/VHDL
mindshare. Synopsys is a close second with 43% + 4% = 47% total mindshare.
The real story here is the *change* in the company totals from 2004 to 2005.
Cadence 2004 total : ############################### 51%
Cadence 2005 total : ############################### 51%
Synopsys 2004 total : #################### 34%
Synopsys 2005 total : ############################ 47%
Mentor 2004 total : ######################### 41%
Mentor 2005 total : ##################### 35%
others 2004 total : ####### 11%
others 2005 total : ### 5%
That is, Cadence use has remained constant while Synopsys use went noticably
up and Mentor use went slightly down. I'm not sure why this is, but this
result stands out in particular because so many of the 2004 vs. 2005 stats
don't change in many other parts of this report.
Another thing you'll notice is that if you total *all* the Verilog/VHDL
simulator use for *all* simulators for 2004, it comes to a grand total of
137%. It also comes to a grand total of 138% for 2005. Why? Because your
average simulator user has more than one brand of Verilog/VHDL simulator
that he uses. (I explained this earlier in the "Mindshare vs. Marketshare"
part of this report.)
2004 - "Does your project do mixed Verilog/VHDL simulations?"
Verilog only : ######################### 49%
mixed : ####################### 45%
VHDL only : ### 6%
2005 - "Does your project do mixed Verilog/VHDL simulations?"
Verilog only : ############################## 59%
mixed : ################### 38%
VHDL only : # 3%
Interesting shift here. Over the past year, the world has gotten more
focused on Verilog -- and less "mixed", less "VHDL only" simulations.
Cadence/NC-Verilog 5.4 (Verilog), Synopsys/VCS7.0 (Verilog).
- Masato Inogai of Fujitsu
Verilog - Synopsys for designers, Cadence for verif. No VHDL.
- Ross Smith of NuCore Technology, Inc.
ModelSim most often; VCS, NC-Sim/NC-Verilog occasionally.
Yes we do mixed mode because we write models at client's request in
the client's requested language. Our testbenchs are most frequently
written in Verilog (our preferred language). That is why we run
co-simulations from time to time.
- Nuno Franca of Chipidea
We use Synopsys VCS mostly, we also use Mentor ModelSim, but prefer
VCS for speed.
- Ian Perryman of Altera
Synopsys VCS 99%
Fintronix Finsim 1% (experimental only)
- Kea Hunt of Nazomi Communications
Our primary simulator is ModelSim (far better GUI, debug, stability),
we also have a few licences VCS/VCS-MX (better performance, GUI and
debug capabilities improved quite abit lately). We do mixed language
sims, we are primarily a VHDL design house, but integrate Verilog IP.
- [ An Anon Engineer ]
Cadence NC-Verilog, no VHDL at all.
We do however convert our RTL-to-C with the freeware Verilator tool,
this gives us a big boost in cycles/second simulated and every
software developer can run this cycle accurate model on his/her own
PC without the need for a license. This is a magnificent tool for
software performance analysis on our CPU.
- Jean-Paul van Itegem of Philips Semiconductors
We use Synopsys VCS. No, we do not do mixed Verilog/VHDL simulations.
- Dave Ferris of Tundra Semiconductor
Synopsys VCS, no mix
- [ An Anon Engineer ]
VCS. No mixed - all Verilog
- Dan Joyce of Hewlett-Packard
We have been using Mentor ModelSim. We are now migrating to
NC-Verilog/VCS for strategic reasons. We don't run mixed simulations
because we are 100% Verilog.
- Juan Carlos Diaz of Agere Systems
Mentor ModelSim. Mixed - yes! Few IPs are in Verilog and the rest
in VHDL.
- Karthik Kandasamy of Wipro
We primarily use NC-Sim, mixed, because our company became language
neutral in 2000 and also we get IP with either language lineage. We
also use a few seats of MTI because our Analog Mixed Signal design
flow uses Eldo.
- [ An Anon Engineer ]
Cadence NC-Verilog and Synopsys VCS. No VHDL.
- Christian Mautner of Integrated Device Technologies
We use VCS for our Verilog simulations. A previous project used both
Verilog and VHDL. We used ModelSim in that instance as the mixed
language (VCS-MX) was extremely unwieldy.
- [ An Anon Engineer ]
Cadence NC-Sim and Icarus Verilog. Yes we do mixed signal simulation.
Mainly Verilog but some cores we use are written in VHDL.
- Luke Darnell of G2 Microsystems
Using Mentor ModelSim. Have VHDL, Verilog, SystemC licenses. Design
entry and current testbenches are VHDL. Back-annotated sims use
Verilog netlists. No current mixed-lang RTL sim except for a small
Verilog IP models from FPGA libraries. Nothing against it.
- Jan Johnson of Rockwell Collins, Inc.
VCS and some NC-Verilog. No mixed.
- Sandro Pintz of Portal Player, Inc.
VCS (Synopsys), No we do not do mixed sims.
- [ An Anon Engineer ]
VCS. No mixed mode.
- [ An Anon Engineer ]
We use Cadence simulators. Yes we use mixed-HDL, mainly because other
groups in the company use Verilog, so to simulate with their ASICs we
use a mixed-HDL simulator.
- Samuel Irlapati of Unisys
We use both VCS and NC-Verilog for Verilog Simulation. No mixed mode.
- [ An Anon Engineer ]
ModelSim SE. Design reuse from another branch of company who had
previously used Verilog, while we all now standardized on VHDL.
- [ An Anon Engineer ]
VCS. No mixed languages.
- Jonathan Craft of McData Corp.
We use ModelSim. When we start a new project, we pick the language
(VHDL or Verilog) based on availability of models and synthesizable
IP, then stick with that language choice throughout the end of a
project. Sometimes, though, we're forced to do mixed-language
because we change IP or re-target a different foundry that only
provides Verilog, and the rest of our design is in VHDL. If I had
my preference, everything would be in Verilog.
- Tom Mannos of Sandia National Labs
Cadence NC-Sim; we do mixed Verilog/VHDL due to some IPs available
only in VHDL.
- [ An Anon Engineer ]
VCS, only Verilog
- Michael Roeder of National Semiconductor GmbH
ModelSim. We have mixed mode capability. Our designs often have
both VHDL and Verilog elements.
- [ An Anon Engineer ]
Cadence NC-Verilog. We do not do mixed sims (Verilog only).
- [ An Anon Engineer ]
Synopsys VCS. No mixed Verilog/VHDL.
- Mark Lancaster of Freescale Semiconductor
NC-Sim. Yes mixed due to macros developed in different design centers.
- [ An Anon Engineer ]
Cadence Verilog and VHDL. We have existing an existing design in VHDL
but plan to use Verilog for the next project. Making a configurable
testbench is easier in Verilog (i.e. using `ifdef) and thus we use a
top level Verilog wrapper even with a VHDL DUT.
BTW, most consider it a mistake that our company originally went with
VHDL. As our lead designer put it: "it sure is easier to get someone
to switch from VHDL to Verilog than the other way around".
- Jeff Koehler of Ammasso, Inc.
We used an internally developed cycle-based simulator for VHDL
designs. Some event-based simulations done using NC-Sim.
- [ An Anon Engineer ]
No mixed mode. We use VCS Verilog internally and purchased IP has
been available in Verilog.
- [ An Anon Engineer ]
I'm using Synopsys VCS primarily -- and no mixed mode.
- George Gorman of LSI Logic
VCS-MX. Mixed Verilog/VHDL
- [ An Anon Engineer ]
Synopsys VCS
- Larry Davidson of Ario Data Networks
Cadence NC - verilog; No mix.
- [ An Anon Engineer ]
We use NC-Verilog (unfortunately). No mixed simulators.
- Michiel Vandenbroek of China Core Technology Ltd.
We use Cadence NC-Sim. We do run mixed VHDL/Verilog simulation
mainly because of integrating a wide number of IPs in different
langages.
- Olivier Haller of STMicroelectronics
Mainly ModelSim but we also occasionally test with NC-Sim and VCS-MX.
We do mixed language simulations; our IP cores are written in VHDL
but we have to supply VHDL and Verilog support files (wrappers and
such) to our customers so simulating a VHDL core in various Verilog
top level is part of the regression test suite.
- [ An Anon Engineer ]
We use ModelSim, with mixed Verilog and VHDL for netlists from ASIC
vendor, but VHDL is our main development language. We also do mixed
SystemC/VHDL simulations.
- Frank Vorstenbosch of Telecom Modus Ltd.
Mentor ModelSim. Yes we do use mixed verilog/vhdl. Only in two
cases though. We use mixed simulation for ASIC netlist simulation
(if emulation is not taking place and the top level of the design
is complex) and where FPGA makers only provide IP models in Verilog.
- [ An Anon Engineer ]
No mixed, only Verilog simulations.
- Jiye Zhao, Chinese Academy of Sciences
VCS-MX. Yes, we are a SoC-shop and we get IP that comes from all
parts of the world.
- [ An Anon Engineer ]
Cadence NC-Verilog. Verilog only. No mixed Verilog/VHDL.
- [ An Anon Engineer ]
VCS with System Verilog and Mentor ModelSim with System Verilog
- Cliff Cummings of Sunburst Design
We're currently using Synopsys' VCS Verilog simulator. We expect to
switch to Mentor ModelSim Verilog simulator within the next 3 months
due to lower cost and PSL support. Synopsys doesn't support PSL and
doesn't seem to have it on their product development roadmap. We're
a Verilog-only shop, so no mixed Verilog/VHDL simulations.
- [ An Anon Engineer ]
Synopsys VCS
- Peng Hong of Datang Microelectronics China
Mentor ModelSim - because it supports Verilog, System Verilog, VHDL,
and SystemC.
- Tom Moxon of Moxon Design
Verilog, mostly Simucad. 32/64 bits. Acquired by Ivan/Silvaco
- [ An Anon Engineer ]
ModelSim SE / VHDL.
- Jay Brown of Top Layer Networks
Verilog NC-Sim 5.4 No mixed. Completely switched over to Verilog
from VHDL.
- [ An Anon Engineer ]
Synopsys VCS-MX. Yes we use mixed languages because (1) we are VHDL
based for both RTL and test benches but physical design interface is
Verilog and (2) some IP models are only available as Verilog.
- [ An Anon Engineer ]
We use NC-VHDL for most of our simulations. On my last project, I did
some mixed-mode simulations, primarily to speed up the simulation times
(we used Verilog models instead of the VHDL models). We noticed almost
a 2x speed difference.
- Tony Lanier of Harris Corp.
Mentor Graphics Modeltech. Yes mixed sims. All of our RTL is VHDL,
some of our netlist is in Verilog. Why? Verilog netlist run faster
than VHDL netlist. We only do this for speed, because it grabs both
two simulator licenses to do mixed language.
- [ Kenny from Southpark ]
Cadence NC-Verilog. Verilog only.
- Andrew Peebles of Cortina Systems
Cadence NC-Sim. Yes we do mixed Verilog/VHDL simulations. We were
a VHDL house purchased by a company that uses Verilog.
- [ An Anon Engineer ]
Simulator: NC-Sim by Cadence. No mixed Verilog/VHDL simulations;
only Verilog.
- Stefano Traferro of STmicroelectronics
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