( DVcon 05 Item 3 ) --------------------------------------------- [ 10/25/05 ]
Subject: SystemC
CADENCE SYSTEMC -- Overall SystemC adoption is only at 42% in 2005. Pretty
much only the verification/modeling crowd are using SystemC. Few hardware
designers are using/thinking SystemC as an implementation language.
2004 - "Do you see your project using SystemC in the next 6 months?"
not in the
next 6 months : ################################## 68%
yes we will : ################# 32%
2005 - "Do you see your project using SystemC in the next 6 months?"
not in the
next 6 months : ############################# 58%
yes we will : ##################### 42%
Asking only those in 2004 who are or will be using SystemC:
2004 - "Are you using SystemC for high level modeling,
or verification, or for design?"
high level modeling : ######################## 72%
verification : ##################### 64%
design : ## 5%
Asking only those in 2005 who are or will be using SystemC:
2005 - "Are you using SystemC for high level modeling,
or verification, or for design?"
high level modeling : ####################### 70%
verification : ##################### 62%
design : ## 7%
SystemC-based design and synthesis is still considered experimental by most
chip designers in the 2005 group; hence that 7% for design.
2005 - "Whose SystemC tools are you using?"
Cadence NC-SystemC : #################################### 36%
Cadence TestBuilder : #### 4%
CoWare : ### 3%
Free OSCI : ################################# 33%
Mentor ModelSim : ################ 16%
Synopsys CoCentric : ########## 10%
Mentor CatapultC : # 1%
Forte Cynthesizer : # 1%
Synfora Pico : # 1%
If you add up the Cadence "family" of SystemC wares (NC-SystemC, TestBuilder,
and CoWare) they own this space in 2005 with 43% mindshare. Let me say that
another way -- Synopsys only has 10% and Mentor 17% -- making them dwarves
compared to Cadence's 43% presence in the 2005 SystemC world.
Currently using SystemC for verification. Cadence SystemC.
- Ross Smith of NuCore Technology, Inc.
SystemC - no.
- Elchanan Rappaport of Lynx Photonic Networks
No. Certainly not in the next 6 months and probably never. SystemC
is a minimal solution looking for a maximal problem.
- Kevin Jones of Rambus
We're using Cadence's SystemC extensions for some of our verification.
- Niels Reimer of Agilent
Our project currently has about 200,000 lines of SystemC code which
is used for verification. We use Cadence NC-SystemC.
- [ An Anon Engineer ]
Yes. High level modeling and verification. OSCI and Cadence
- Menno Lindwer of Philips Semiconductors
We are using SystemC for verification. Using Cadence NC-SystemC.
- [ An Anon Engineer ]
Yes, currently using SystemC as the behavioural, not cycle accurate,
reference model. Cadence NC-Sim co-simulation (SystemC behav + VHDL
with mixed RTL) for verification. OSCI environment used separately
for SystemC architectural and reference model development.
- Bob Warren of STmicroelectronics
We are using Cadence's CVE (TestBuilder) SystemC for most of the
stimulus and checking; very little HDL testbenches. Goal is to have
even small test benches use SystemC. The SystemC random stimulus
generation is workable, although not as terse as a dedicated HVL such
as Vera (and I suspect 'e').
In addition, we are using Cadence's VIC (Verification Interfaces and
Components library). VIC does a great job of wrapping up the
communication between components so you are transaction-based instead
of procedural. It also nicely hides the tedium of Cadence SPI
transaction logging, which we are using heavily to post-process our
functional coverage results. Our designers also like seeing our
stimulus/response transactions side-by-side with their HDL waveforms.
- Jeff Koehler of Ammasso, Inc.
We use TestBuilder (which is now part of SystemC) for a TB environment
- [ An Anon Engineer ]
We make extensive use of both TestBuilder Classic and TestBuilder/SCV
for system-level verification, packet generation and compliance
checking. SystemC is being proposed as an architectural model for
our algorithmic designs. We have no plan to use SystemC for RTL
design of internal IP.
- [ An Anon Engineer ]
No SystemC right now, though another group is playing with it in
their project.
- Tom Mannos of Sandia National Labs
Using SystemC/TestBuilder for verification. Tools used are Cadence.
- [ An Anon Engineer ]
Yes, we are using SystemC for a DSP design for 2 years. Originally it
was used for pure designing, and the abstract level went down to gate
level. Now we move SystemC up to the cycle-accurate level for
architecture designing and verification. We model not only DSP, but
also for components and peripherals used in the project, such as DMAC,
SDRAM, SDRAM controller, vectored interrupt controller, etc.
Currently we use Cadence NC-SystemC, SystemC simulator from SystemC
Forum, and MaxSim from ARM.
- Alan Su of Industrial Technology Research Institute Taiwan
We are not currently using SystemC. We intend to use SystemC
seriously quite soon, probably Cadence NC-SystemC as well.
- [ An Anon Engineer ]
We are using SystemC now, for high level simulation, architectural
modeling and to allow SW development on our in-house processors. We
have SystemC for ModelSim, and also use the OSCI kernel 2.0.1.
- Frank Vorstenbosch of Telecom Modus Ltd.
Yes. For high level modeling and architectural exploration. We are
looking at it for verification. We have used Cadence NC-SystemC and
OSCI reference simulator.
- [ An Anon Engineer ]
On few projects, we use SystemC for verification/testbenching.
We use Cadence NC-SystemC/SimVision.
- [ An Anon Engineer ]
No, I do not see us using SystemC ever.
- John Zook of Stargen
My group is involved in creating SystemC simulation models. We have been
working on this since the advent of SystemC modeling. Prior to this we
had our own modeling framework. These models are used for verification of
software, architectural exploration. We have our internal customised
environment comprising of SystemC-SCV compliance to OSCI. We also use
Cadence LDV for NC-SystemC simulations.
- [ An Anon Engineer ]
We are now using SystemC for high level modeling. We're using the
OSCI reference simulators, NC-SystemC and are looking at CoWare.
- [ An Anon Engineer ]
No.
- Mark Lancaster of Freescale Semiconductor
Yes. Using SystemC on current project as a HVL/testbench only. Using
Cadence SCV tools.
- [ An Anon Engineer ]
We are already using SystemC and only for architectural exploration.
System Studio from Synopsys and OSCI.
- Sandro Pintz of Portal Player, Inc.
Yes, we use SystemC for high level modeling. We use ModelSim for
SystemC simulation.
- [ An Anon Engineer ]
We are seriously considering SystemC for our high level modeling.
- Samuel Irlapati of Unisys
No SystemC within the next 6 months. But an independent verification
team used Cadence NC-SystemC for verifying one of the block of our
last ASIC.
- [ An Anon Engineer ]
No, We just use the standard C for high level modeling.
- Jiye Zhao, Chinese Academy of Sciences
No.
- Dave Ferris of Tundra Semiconductor
Yes. We have been using SystemC since 2002. We use SystemC for
system modeling and DV. We have been running Verilog, VHDL, SystemC
cosimulations for about 3 years. We have verified a multiprocessor
design using that approach and are on our second silicon pass (mostly
due to a library problem). We are in the middle of our second design
using this methodology. We are using generic SystemC without any
vendor-specific tools except for ModelSim. All our software, DSP,
and RTL engineers are coming up to speed on SystemC. We deliver
SystemC models to our systems group. The models run on Windows or
Linux. We're shopping for SystemC compilers for quick FPGA synthesis.
- Jeff Clark of Starkey Labs
No, SystemC is not even an experiment here.
- [ An Anon Engineer ]
No, No.
- Nuno Franca of Chipidea
No
- [ An Anon Engineer ]
Do not intend to use SystemC at this time. I do plan to use C-models
co-simulating with System Verilog code through the new System Verilog
DPI (Direct Programming Interface) and have already run some simple
models this way.
- Cliff Cummings of Sunburst Design
No. We just went thru evaluations of SystemC versus System Verilog
and decided that System Verilog was easier to learn and use (for
us anyway.)
- Tom Moxon of Moxon Design
Yes to SystemC for verification. We used SystemC with VCS DKI on a
recent project for CO-SIM and other verification tasks. We will be
using SystemC with Incisive and their VIC libraries on a new project.
- [ An Anon Engineer ]
No SystemC within next 6 months.
- Dan Joyce of Hewlett-Packard
Yes, fully SystemC on next project within 6 months
We have started SystemC modeling for verification partially on current
project. Cadence Incisive + Coware
- [ An Anon Engineer ]
Yes, for modeling signal processing hardware. Using MTI.
- Arun Chaddha of Tenesix, Inc.
Yes. We currently use SystemC for verification but not on my project.
My next project will use it.
- [ An Anon Engineer ]
No SystemC. I was suprised that DVCon organizers were pushing SystemC
for next year's focus.
- George Gorman of LSI Logic
We use SystemC for detailed dynamic performance model (was originally
our system architecture model). Don't use it for DV, although if I
was starting from scratch at this point I would seriously consider it.
- [ An Anon Engineer ]
We are using SystemC for transactionnal level modeling.
- Olivier Haller of STMicroelectronics
No.
- Michiel Vandenbroek of China Core Technology Ltd.
No, no SystemC whatsoever.
- [ An Anon Engineer ]
No SystemC. Answer based on experimental internal evaluation.
- [ An Anon Engineer ]
No
- Karthik Kandasamy of Wipro
No plans on using SystemC.
- Juan Carlos Diaz of Agere Systems
Yes. Synopsys CCSS 2003.12
- [ An Anon Engineer ]
No SystemC.
- Stefano Traferro of STmicroelectronics
Yes. For verification. We're using the free & Open SystemC library.
- Christian Mautner of Integrated Device Technologies
No
- William Mills of Northrop Grumman Corp.
We are using SystemC for high level modeling. The purpose is SoC
architecture evaluation before the real design. The tool is Synopsys
System Studio.
- Peng Hong of Datang Microelectronics China
No SystemC. We at most could be interested in making a SystemC model
of our CPU available to our customers. But if you ask me the
Verilator model in a SystemC wrapper is probably the best approach
there.
- Jean-Paul van Itegem of Philips Semiconductors
We use SystemC quite extensively for modeling, and in a more limited
extent to provide a model to verify against for Specman 'e'
verification. Most of our SystemC work is done using the free
libraries plus gcc.
- [ An Anon Engineer ]
Using SystemC for modeling and verification. ModelSim, MS Visual C++.
- Greg Tumbush of Starkey Labs.
No.
- Jonathan Craft of McData Corp.
No, when we played with SystemC, the learning curve seemed too high.
- [ An Anon Engineer ]
No. Designs are too small to justify SystemC for validation.
- Mike Bly of World Wide Packets
No use whatsoever for SystemC.
- Eric Holmberg of Mahi Networks, Inc.
My current project will not use SystemC. There has been some talk
about using it for other future projects, but so far, it's just talk.
- Tony Lanier of Harris Corp.
Yes. We will use SystemC to writing bit-accurate verification
reference models, just like the last project. We are using the
plain SystemC.
- Henry So of Mobilygen
No SystemC. We will stick with C/C++ and Verilog. We don't see much
advantage on using anything else.
- J.D. Allegrucci of GiQuila Corp.
Yes, currently use SystemC for architecture modeling and golden model
for verification. Just use OSCI SystemC with GNU tools set.
- Tuan Luong of Integrated Device Technologies
No. We are not using SystemC for anything today and are unlikely to
use it in the next 6 months.
- Tom Ebzery of Hifn, Inc.
No
- Michael Roeder of National Semiconductor GmbH
Have the OSCI and ModelSim SystemC tools installed. Just getting
started. Adapting a C model to SystemC for modeling our environment.
Hope to reuse that model during verification. Wrote too much RTL
first for FPGA prototype, may work backward and create SystemC models
from the RTL to speed things up.
Hoping to do as much simulation possible in SystemC only, doing co-sim
with VHDL design when necessary. With all SystemC, there is no license
limitation on OSCI. Since OSCI doesn't do VHDL, I tie up $$$ licenses
with mixed-lang sims.
- Jan Johnson of Rockwell Collins, Inc.
Index
Next->Item
|
|
