( DVcon 05 Item 4 ) --------------------------------------------- [ 10/25/05 ]
Subject: System Verilog
SYNOPSYS MESSES UP -- Last year users were waiting for Cadence and Mentor to
support System Verilog in their tools. Oops! Everyone *assumed* Synopsys
would have System Verilog fully implemented in the SNPS flow -- wrong! This
year Synopsys *should* deliver on System Verilog, but until then it's still
only 1 in 5 engineers using/thinking System Verilog. Oops.
2004 - "Do you see your project using System Verilog in the next 6 months?"
not in the
next 6 months : ####################################### 79%
yes we will : ########### 21%
2005 - "Do you see your project using System Verilog in the next 6 months?"
not in the
next 6 months : ######################################## 81%
yes we will : ########## 19%
Asking only those people who are or will be using System Verilog:
2004 - "Do you plan on using the System Verilog
design or the verification extentions, or both?"
verification : ######################### 63%
design : ## 6%
both : ############# 32%
2005 - "Do you plan on using the System Verilog
design or the verification extentions, or both?"
verification : ############################ 70%
design : ## 5%
both : ########## 26%
And asking those people in 2005 who are or will be using System Verilog:
2005 - "Whose System Verilog tools are you using?"
Synopsys VCS : ################################ 79%
Mentor ModelSim : ###### 15%
Cadence : ## 6%
That 79% says it all. Officially System Verilog is an open standard, but
with such dominance in that space, it's obvious why a lot of people use
the phrase "Synopsys System Verilog".
(Interestingly, despite its slow current adoption, if you look in the
"the Future of Specman 'e' and Vera" section of this census, you'll find
the vast majority of users think that System Verilog will replace Specman
and Vera within 5 years. Check it out.)
Yes, mainly for design purposes, but you do still have to be careful
because there are some tools that have issues dealing with System
Verilog. Synopsys tools support it just about everywhere for the
design extensions, and are expected to support all the verification
extensions soon.
- K.C. Buckenmaier of Hifn, Inc.
Yes to some extend. We will definitely start with VCS NTB soon within
6 months if System Verilog is matured, we will add System Verilog test
bench constructs since they are interoperable with Vera in VCS.
- Azeez Chollampat of PLX Technology
Yes. We will use System Verilog from Synopsys.
- Henry So of Mobilygen
No.
- Dave Ferris of Tundra Semiconductor
No, we don't have plan to use System Verilog.
- Pine Yan of ESS Technology, Inc.
System Verilog - no.
- Elchanan Rappaport of Lynx Photonic Networks
No.
- Jiye Zhao, Chinese Academy of Sciences
We are using System Verilog for our current project. Use is limited
to design extensions except for assertions. We use Synopsys VCS for
our System Verilog designs.
- [ An Anon Engineer ]
No.
- Frank Vorstenbosch of Telecom Modus Ltd.
No. We are far too risk averse to move to System Verilog in the
near future.
- [ An Anon Engineer ]
Yes. Mainly for verification, BFM design etc, not design. Hey, it's
included for free in VCS. Can't hurt to use it.
- Rajen Ramchandani of Mindspeed Technologies
Yes. We'll be using System Verilog for both design and verification.
Currently we're using VHDL for design and verification. We've been
using Mentor ModelSim and will continue to use it. The ModelSim 6.1
beta is just out, with better SV 3.0 support, but it's not completely
there just yet. ModelSim comes with System Verilog -- no additional
cost there.
- Tom Moxon of Moxon Design
Not within 6 months. Probably within 12 months. Want to use for
verification. Need object oriented features for maintainability.
Probably would stick with Cadence System Verilog for business reasons.
- [ An Anon Engineer ]
No
- Peng Hong of Datang Microelectronics China
No.
- Pascal Gouedo of STmicroelectronics
We don't use System Verilog currently. I'm intending on having a play
with it when I get time. We're mostly a VHDL house, so System Verilog
isn't such a natural progression.
- [ An Anon Engineer ]
Yes to System Verilog. We're a little concerned about full tool
support (code coverage tools appear to be a bit behind the curve) but
if that is resolved we'll certainly be using the design constructs in
our next project.
I very much doubt that the verification extensions will be fully
functional (RELIABLE) within the next 6 months. We're planning on
using VCS, and Novas Debussy (if it works with System Verilog) for
verification & debug. Synopsys DC for synthesis.
- Jonathan Craft of McData Corp.
Yes. We're already moving to System Verilog incrementally on both
design and verification fronts (eg. use of the new "bit" type and also
SV assertions). That's for real use, not experimental. We're
currently using Synopsys VCS, but will switch to Mentor ModelSim
shortly.
- [ An Anon Engineer ]
Yes System Verilog, for verification.
- Stefano Traferro of STmicroelectronics
No.
- Menno Lindwer of Philips Semiconductors
There's efforts to get started on System Verilog. Since it is bundled
with the VCS package we have. But the bottleneck is getting engineers
to write the new System Verilog testbenches.
- [ An Anon Engineer ]
No, No.
- Nuno Franca of Chipidea
No, we can do most of what we need to do with Verilog-2001. We're
reluctant to add System Verilog constructs because they would likely
break some of our legacy tools.
- Tom Mannos of Sandia National Labs
No
- [ An Anon Engineer ]
No
- William Mills of Northrop Grumman Corp.
Yes. We will move to System Verilog as soon as it supports all the
Vera constructs we use - for performance gains. We are seeing pretty
good performance from Vera now though.
- Dan Joyce of Hewlett-Packard
Yes. System Verilog verif extension.
- [ An Anon Engineer ]
No
- Ross Smith of NuCore Technology, Inc.
Yes, System Verilog on both design and verification. (The only thing
stopping us right now is EDA support for the verification aspects.)
- [ An Anon Engineer ]
No
- Samuel Irlapati of Unisys
No System Verilog.
We are evaluating the System Verilog design Constructs which are very
promising, probably will be used within a year dependent on tooling
support from EDA, FPGA & ASIC vendors. We are less interested in the
System Verilog Assertions and have limited interest in verification
aspects of the language.
- [ An Anon Engineer ]
No.
- Jean-Paul van Itegem of Philips Semiconductors
No, with the exception of System Verilog Assertions sprinkled in
the code.
- Christian Mautner of Integrated Device Technologies
No System Verilog in the next 6 months.
- [ An Anon Engineer ]
No. Just experimenting.
- Kea Hunt of Nazomi Communications
No.
- Lyle Kraft of Agilent
Not in the next 6 months, but soon after that.
- Dan Steinberg of Integrated Device Technology
No, not within the next 6 months. We plan to use System Verilog in the
longer term, for both verification and for design (one language etc).
- [ An Anon Engineer ]
No
- Jan Johnson of Rockwell Collins, Inc.
No. We plan to evaluate System Verilog within 6 months.
- [ An Anon Engineer ]
Yes, we use System Verilog on a very limited basis now. We use
Synopsys.
- Tom Ebzery of Hifn, Inc.
Yes maybe System Verilog. Not using it yet, but would like to use it for
the verification extensions.
- George Gorman of LSI Logic
No
- Michael Roeder of National Semiconductor GmbH
Yes - verification extentions. VCS-MX (if Synopsys implements in time)
- [ An Anon Engineer ]
No plans of using System Verilog.
- Juan Carlos Diaz of Agere Systems
No
- Greg Tumbush of Starkey Labs.
Not in the next six months, but we're headed that way.
- [ An Anon Engineer ]
No.
- Olivier Haller of STMicroelectronics
Not using System Verilog currently for design primarily because of
poor Formality support. However, any new projects will probably
use System Verilog for design (structures, interfaces, etc.)
- Matt Weber of Silicon Logic Engineering, LLP
Yes, Cadence System Verilog.
- [ An Anon Engineer ]
No. Designs are too small to justify System Verilog for validation.
- Mike Bly of World Wide Packets
Yes, we are very likely to use System Verilog in the next 6 months,
particularly the verification extensions. We'd be using it now except
it's not quite stable yet.
- Kevin Jones of Rambus
YES. We do some System Verilog 3.1a now, and expect extensive use
in next 3 months.
- Eric Holmberg of Mahi Networks, Inc.
No. Half the people on our verification team have very strong OO SW
backgrounds, and retch at the thought of using System Verilog for their
primary development language, plus having no ancillary SW development
tools or libraries to leverage.
- [ An Anon Engineer ]
I seriously doubt we will ever use System Verilog. We use mostly
VHDL for all of our source code and testbench environments, with
good success.
- Tony Lanier of Harris Corp.
No.
- Mark Lancaster of Freescale Semiconductor
No
- John Gray of Atmel
No - not using, no - not going to use
- [ An Anon Engineer ]
I love the System Verilog additions and am looking forward to using
them on a future product. Given all the troubles that Verilog 1995
has suffered through the years, a compliance suite for System
Verilog would certainly accelerate adoption. Until I can depend on
System Verilog, I'll be sticking with the old reliable stuff.
- Niels Reimer of Agilent
No
- Marshall Johnson of Movaz Networks
No
- Ba Nguyen of SonoSite, Inc.
No. we are evaluating TB features and benchmarking against Specman "e".
- [ An Anon Engineer ]
No.
- Michiel Vandenbroek of China Core Technology Ltd.
No, I see no future in System Verilog.
The C/C++ basis for SystemC seems the obvious way to go for a richer
modelling language, especially when early architectural development
has not yet made the distinction between a hardware implementation
or a software implementation (or even the selection of a CPU/DSP).
- Bob Warren of STmicroelectronics
No
- Karthik Kandasamy of Wipro
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