( DVcon 05 Item 5 ) --------------------------------------------- [ 10/25/05 ]
Subject: Verisity Specman "e", Synopsys Vera, SystemC SCV, JEDA
SYSTEMC SCV UP; JEDA DEAD -- It's spooky how close the 2004 and 2005 stats
were for the Vera vs. Specman "e" battle. It's deja vu all over again!
2004 - "What do you think about Verisity Specman 'e' vs. Synopsys
Vera? Does your project use either of these?"
don't use : ########################################## 42%
Verisity Specman "e" : ############################ 28%
Synopsys Vera : ########################## 26%
we use both : ### 3%
2005 - "What do you think about Verisity Specman 'e' vs. Synopsys
Vera? Does your project use either of these?"
don't use : ########################################### 43%
Verisity Specman "e" : ############################# 29%
Synopsys Vera : ########################### 27%
we use both : # 1%
It's those non-Vera/non-Specman equivalents that were interesting:
2004 - "What about alternatives like JEDA or SystemC SCV?"
we use SystemC SCV : ######### 9%
we use JEDA : # 1%
2005 - "How about alternatives like JEDA or SystemC SCV?"
SystemC SCV : ####### 7%
JEDA : 0%
Synopsys NTB : ####### 7%
I was surpised at the number of people who mentioned Synopsys Native Test
Bench (NTB) even though it wasn't prompted by the question. JEDA officially
died this year. No one's using it. There was some colorful SystemC SCV
commentary, too.
SCV does the job, but it is r-e-a-l-l-y s-l-o-w. Templates on top of
templates, and G++ doesn't really support pre-compiled headers, so it
seems we spend most of our time reading SCV .h files.
- Jeff Koehler of Ammasso, Inc.
SystemC SCV seems adequate for starters, as we climb that curve.
- Jan Johnson of Rockwell Collins, Inc.
SCV is priced right!
- Greg Tumbush of Starkey Labs.
My team avoids "e" like the plague, although other teams in our company
use it happily. No experience with Vera. We transitioned last year
from TestBuilder and a custom C++ environment to SystemC SCV (two
projects so far) with reasonable success.
- [ An Anon Engineer ]
Our co-simulation environment: Specman + SystemC + VHDL.
SystemC SCV is likely to contend with Specman and in the future may
be preferred depending on project requirements.
- Bob Warren of STmicroelectronics
We use SystemC SCV. Tried "e" & Vera. Vera is a big kludge, "e" is
overpriced. I can't see any life to Vera or "e" unless they give
them away. SystemC SCV rocks!
- [ An Anon Engineer ]
At this point this like comparing Greek vs Sanscrit vs Latin. I expect
System Verilog will eclipse them all.
- Eric Holmberg of Mahi Networks, Inc.
Is Jeda still around? I haven't heard from them in a long time. SCV
is an improvement over TestBuilder, but that's not saying much!
- [ An Anon Engineer ]
We are not now & have never used "e" or Vera. We're using SystemC SCV
and are pleased so far. The randomization ablities is very useful.
- [ An Anon Engineer ]
I am pushing for SV verification SVTB (NTB). I don't want Verisity
(which I don't think will survive long). Also trying to stay away
from Vera although we might use some since SVTB is not ready and the
transition should not be so complicated.
- Sandro Pintz of Portal Player, Inc.
Using Native TestBench. Currently NTB is still lacking key
capabilities that exist in Specman and Vera. With the promise
of NTB merging with Vera, it will be more useful.
- [ An Anon Engineer ]
We're using Specman 'e' for RTL design verification. However, we'll
switch to Synopsys NTB for the next project. The switch is purely
decided on cost issue. In the future we're hoping that System
Verilog Verification extension will be the standard.
- Tuan Luong of Integrated Device Technologies
We use Synopsys Vera, but as it gets more popular here people are
switching to Synopsys VCS Native Testbench to save the cost of extra
licenses. NTB is an incredibly useful extention to VCS. Hard to say
whose ahead/behind since we only have knowledge/experience of Vera,
but if Vera is not in the lead there's some truly exceptional products
out there.
- [ An Anon Engineer ]
We would like to be using System Verilog and all of it's SVTB features.
But, it's not quite ready for this project. So, the next best option
is Vera (NTB) as a place-holder for SVTB. I've got to believe that
it's going to be hard for 'e' to survive when the competition is "free"
(assuming you already have a VCS license).
- Dan Steinberg of Integrated Device Technology
In 5 years Cadence will have killed 'e', either on purpose or by running
the Verisity tools and support into the ground.
- Michiel Vandenbroek of China Core Technology Ltd.
We use Specman. Specman is ahead of Vera.
Jeda is not an alternative. SystemC SCV might be ok.
- [ An Anon Engineer ]
We are using Vera only.
- Peng Hong of Datang Microelectronics China
We've been power users of Specman for years. It's still our main
verification tool. I have concerns about the future given its recent
acquisition by Cadence and I see System Verilog becoming the tool of
choice in this space going forward.
- Kevin Jones of Rambus
SystemC SCV is the choice.
- [ An Anon Engineer ]
We use Specman on projects now. Not sure of a comparison vs Vera.
We are also looking at SystemC SCV.
- [ An Anon Engineer ]
Use Specman. Will likely move to SystemC and System Verilog within
the next two years due to Specman being proprietary, single-vendor.
- [ An Anon Engineer ]
We use Specman and SystemC. Specman is clearly ahead of Vera in the
verification space, we added SystemC to our portfolio for cost reasons
more than anything else. With Cadence owning both tools now, I'm not
sure what our direction will be.
- Niels Reimer of Agilent
We use Vera. I have used Specman in the past, and at this point
I think that Vera has almost completely caught up to, if not
surpassed, the capabilities in Specman. With the coming ability
to use System Verilog for serious verification, I don't see much
point in looking at less popular alternatives.
- K.C. Buckenmaier of Hifn, Inc.
I think that these will die off as System Verilog and PSL take over.
We had a visit from our Synopsys sales guys today - and they are
still pushing Vera - but are covering themselves with additional
System Verilog support.
- Tom Moxon of Moxon Design
Verisity Specman - bad software, complicated syntax, obfuscated
principles. I hope it won't survive for long. Used in the past,
not using now and won't be.
- [ An Anon Engineer ]
I have used Vera in one of my previous projects, but felt that it is
hard to use and Specmen E is better than Vera when it comes to ease
of use. Specmen e has lot more features tha Vera. Specmen e is
definitely ahead.
- [ An Anon Engineer ]
We use both, e is far ahead (macros, reusability of language, etc.)
- Michael Roeder of National Semiconductor GmbH
No Specman "e" or Vera.
We will use SCV to build constrainted random test generators.
- Henry So of Mobilygen
We made a choice to go with Vera years ago, mainly because we liked
the way the Vera language looked compared to 'e'. We use Vera
extensively and exclusively, so we're a little biased, but we do
think we made the right choice.
- Jonathan Craft of McData Corp.
When people with different levels of SW background use Vera, there can
be some strife. Those with a high level of SW experience can create
constructs that are overly "elegant" but very hard for a new team member
to understand. Those with less SW experience tend to hack at it and can
get frustrated coming up the learning curve. The key is to have some
Vera experts who are willing to teach. Then create some useful
templates that newbies can work from.
- Dan Joyce of Hewlett-Packard
We use Specman. Specman is ahead - Vera is behind. No alternatives
currently.
- [ An Anon Engineer ]
Both are competetive. We use Vera.
- [ An Anon Engineer ]
We only use Specman for our verification environment. Did not have a
look to other alternatives as we are really happy with its ease of
"e" use and its powerfullness.
- Pascal Gouedo of STmicroelectronics
It is my impression that Vera and "e" are about even. SystemC SCV has
similar capabilities, but is more difficult to use. We used "e" on our
last project and some current projects. Major focus for our future
is SystemC SCV.
- [ An Anon Engineer ]
Both 'e' and 'Vera' were -invented- to create a new market segment for
EDA sales. I have seen features of both and other than the so-called
'random' number generation routines provided by the languages, there
isn't anything significant that you cannot do with Verilog and C/PLI.
In fact, both (at least 2+ years ago) slowed -down- our simulations.
Maintaining 2 language environment (in an eval we did with Vera) was
a nightmare; not to mention the expertise required for 2 languages.
We stuck to Verilog/C and did VERY WELL.
- [ An Anon Engineer ]
I like them both. We don't use them because they cost money and aren't
public domain.
- Ross Smith of NuCore Technology, Inc.
We will be using the NTB subset of Vera for our current project.
- [ An Anon Engineer ]
Yes, Specman
- [ An Anon Engineer ]
We have used both, but are committed to Vera for consistency with our
overall tool flow and the attractive bundling price. We do not see
enough of a difference to justify integrating a point tool. I think
Verisity is ahead because of an early start and some big initial wins.
I think the Synopsys juggernaut will overtake Verisity.
- Dave Ferris of Tundra Semiconductor
Have not used any, but are more likely to use SCV than the others.
- Frank Vorstenbosch of Telecom Modus Ltd.
Yes, We use Synopsys Vera for code converage.
- Jiye Zhao, Chinese Academy of Sciences
We use Vera on targeted projects. I think they have an advantage in
being integrated more closely with verilog.
- [ An Anon Engineer ]
We use Vera in about 90% of designs with significant logic content.
Verification IP in Vera is also reused tremendously. In fact, because
of the size of our designs in the consumer space, we probably reuse
more internal verification IP than internal synthesizeable IP.
- [ An Anon Engineer ]
No - was using Vera but switched away
- [ An Anon Engineer ]
We have limited use of Vera which will trail off.
SystemC SCV and VIC are in our future.
- [ An Anon Engineer ]
Yes, Specman 'e'. SCV is also considered as an alternative but it is
currently too complex and not supported enough.
- Sylvain Boucher of Philips Semiconductor
I've used Specman e and still use it for some projects. I'm using
Vera now on a small project to learn Vera and lead me to System
Verilog -- I like e better than Vera. I hope that System Verilog
is more palatable to designers.
- George Gorman of LSI Logic
Using 'e' on all projects - looking at System Verilog
- [ An Anon Engineer ]
Not using any of them
- [ An Anon Engineer ]
No Specman or Vera by myself. But an independent verification team
used Specman for verifying one of the block of our last ASIC.
- [ An Anon Engineer ]
We use Specman, which is still a step ahead Vera.
- Olivier Haller of STMicroelectronics
No ( we have a complex vhdl based verification library )
- [ An Anon Engineer ]
Verisity Specman ! It's way ahead of VERA.
- Karthik Kandasamy of Wipro
Specman "e" is much easier to learn/ramp-up. The Specman tool is
excellent. We do use Specman as a corporate policy, as Vera
evals/benchmark were not very positive.
- [ An Anon Engineer ]
We use Specman. Vera is certainly behind. System Verilog is Vera.
- [ An Anon Engineer ]
We use Vera. Can't compare with Specman, it's been a long time since
we evaluated that product.
- [ An Anon Engineer ]
We are starting to use Specman "e".
- Juan Carlos Diaz of Agere Systems
We considered JEDA but chose Verisity because it was more mature. We
now use perl scripts to generate test stimulus and measure coverage,
which works for us just as well as 'e'.
- Michiel Vandenbroek of China Core Technology Ltd.
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