( DVcon 05 Item 12 ) -------------------------------------------- [ 10/25/05 ]
Subject: Cadence Verplex, Synopsys Formality, Mentor FormalPro
WALMART -- With no clear winner nor loser in the Verplex/Formality tech war,
the EC game is a business question. Sad. At one time Verplex was *the*
undisputed ruler of the equivalence checking world. Now it's the best
pricing and packaging at the moment who rules. EC has gone Walmart. Sad.
2004 - "What tool do you use for equivalence checking?"
don't use : ########################## 26%
Cadence Verplex : ###################################### 38%
Synopsys Formality : ############################### 31%
Mentor FormalPro : #### 4%
Prover eCheck : # 1%
homebrew EC : #### 4%
2005 - "What tool do you use for equivalence checking?"
don't use : ########################### 27%
Cadence Verplex : ###################################### 38%
Synopsys Formality : ######################################## 40%
Mentor FormalPro : #### 4%
Prover eCheck : ### 3%
homebrew EC : # 1%
In other news, a number of users have said that Mentor FormalPro was being
end-of-lifed. Don't know if that's true or just a widespread rumor.
The baby of the EC industry, Prover eCheck, got some notice, too.
We use Prover eCheck. Our use is mainly comparison of net of layout
before and the back. eCheck's performance is sufficient for our job
and price is inexpensive, so eCheck is better than Formality we think.
- [ An Anon Engineer ]
Equivalence checking. Got burned more than once, by injected bugs from
more than one FPGA synthesis vendor. Looked to equivalence for help.
Cadence/Synopsys/Mentor either weren't interested, or tried but their
FAEs couldn't figure out how to map the FPGA synthesized names.
Prover eCheck worked real well. No automated flow yet, but the manual
flow (with a little effort) got the job done.
- Elchanan Rappaport of Lynx Photonic Networks
We use eCheck from Prover for our quite small designs for Actel FPGAs
and ASICs. It works fine and shows a very good cost/performance
relationship.
- [ An Anon Engineer ]
We use Prover eCheck. Technically decent and the company is far more
responsive than the bigger players.
- Kevin Jones of Rambus
Mentor FormalPro.
- Rainer Mueller of Oasis SiliconSystems AG
Primarily Verplex. Have also used Formality and FormalPro. Verplex
seems to be ahead.
- [ An Anon Engineer ]
FormalPro is a good tool, but no longer supported.
- Bill Dittenhofer of Starkey Labs
Synopsys Formality. Roughly same as Verplex. FormalPro discontinued
and worse than the other two.
- [ An Anon Engineer ]
Used Formality in a past life; liked it well enough. I believe Mentor
FormalPro is the tool du jour here.
- Jan Johnson of Rockwell Collins, Inc.
We had a bad experience with Mentor FormalPro on an ASIC with more
than a million gates. Prover seems good, but at the time, ASIC
vendor library and custom IP support for Prover was not available.
- Brien Anderson of Siemens Medical
We have used both Formality and Verplex and will be using Formality
again on our next project. Both tools got the job done without a great
deal of pain. No one really stands out against the other so for us the
decision to return to Formality was a matter of consolidation on a
Synopsys tool chain.
- Tom Ebzery of Hifn, Inc.
We use Formality. I still think Verplex/Cadence is ahead.
- Brad Sonksen of QLogic
Formal verification is very important in our flow. We use both
Verplex LEC and Formality. LEC is better than Formality.
- Pine Yan of ESS Technology, Inc.
We use Formality because we got a good price and had existing scripts.
Verplex was preferred as the technical leader, but it was too $$ for
a poor company like us.
- [ An Anon Engineer ]
We use both Verplex and Formality. Verplex is slightly easier to use,
but neither is perfect.
- Jean-Paul van Itegem of Philips Semiconductors
We use Formality for equivalence checking; though we prefered Verplex.
The main difference is ease of debugging. Verplex is much better.
- [ An Anon Engineer ]
We use mainly Formality, but for critical datapath Verplex Conformal
is more effective.
- [ An Anon Engineer ]
We use Synopsys Formality because we need to verify Synopsys DesignWare
implementations. Sometimes, though, it feels like we're hiring Enron to
be our independent auditor...
- Tom Mannos of Sandia National Labs
I used Formality. We had done an evalution of Formality, Verplex and
FormalPro about a year ago. The 3 tools were doing what we needed but
Verplex was too expensive and FormalPro had very few custimers at that
time so we were concern about the future of the tool.
- [ An Anon Engineer ]
Mostly Formality, although Verplex does a better job on a few designs.
Formality has a similar User Interface to other Synopsys tools and SVF
is a reasonable way of passing "hints" from DC to Formality to speed
up matching and datapath verification. With all the advanced
optimization that DC does, like datapath merging and retiming, it is
hard for equivalence checkers to keep up, especially without something
like SVF. I think this is a challenge for Verplex.
- John Busco of Nvidia
Verplex.
- [ An Anon Engineer ]
No equivalence checking here. (manly grunt).
- Dan Joyce of Hewlett-Packard
Both Formality and Verplex LEC. They are comparable.
- [ An Anon Engineer ]
Cadence Conformal for logic equivalence checking. I believe Conformal
is still ahead especially the capability to handle datapath intensive
designs (big multipliers etc).
- [ An Anon Engineer ]
We use Cadence Verplex. Have used it for years (back when it was
only Verplex. Do not see us switching. They have been the leaders,
but I would expect the others are catching up. Little reason for
us to change, however, given our familiarity with the Verplex tool.
- [ An Anon Engineer ]
Formality. We think Formality is ahead.
- Dave Ferris of Tundra Semiconductor
We use Formality for ASICs; Verplex for FPGAs. I'd say Verplex is
ahead of Formality due to their better support for FPGAs.
- [ An Anon Engineer ]
We use Cadence Verplex. Verplex & Formality are the front runners.
- [ An Anon Engineer ]
We switched to Verplex a while ago because of concern that Design
Compiler and Formality might have the same problems understanding
designs, but we're shifting some projects back to Formality now that
Synopsys seems to have addressed those concerns.
- [ An Anon Engineer ]
Cadence Verplex is used here, and has done a very good job for use.
Have to say it is ahead.
- [ An Anon Engineer ]
Use Verplex but not familiar with it.
- [ An Anon Engineer ]
We use Formality but will probably switch for Verplex soon. We've
had too many false positives with Formality to make it useful and
Verplex is a lot more useful.
- [ An Anon Engineer ]
Verplex and Formality. Verplex has the consensus of easier to debug.
But Formality is needed for certain verification where you enable
DC-Ultra to do register retiming, where the equivalence has been
altered. In my opinion this is like a cheat sheet, and has a degree
of letting the fox guard the hen house. But how else can you do EC
for blocks that was synthesized agressively using these sophisticated
synthesis operations? (Without the cheat sheet, the EC tool can't
determine which way is up or down!)
- [ An Anon Engineer ]
None.
- [ An Anon Engineer ]
Formality and Conformal (Cadence) Verplex
- Jiye Zhao, Chinese Academy of Sciences
I've always used Verplex. I did a big evaluation some time ago at
my previous company and Verplex was the only one that worked. I've
heard that it's gone downhill since Cadence bought them. There's
a big surprise.
- [ An Anon Engineer ]
We currently use Synopsys Formality, but it has terribly slow support
for new language constructs. We went through hell with Verilog 2001,
and expect the same for System Verilog. We don't count the existing
Formality SV syntax "translator" as real support for System Verilog.
We'll explore Verplex Conformal before considering any renewal of
Formality licenses. Conformal claims System Verilog support; TBD if
that claim is real.
- [ An Anon Engineer ]
We use Formality. I have noticed some problems with it recently.
It seems to be lagging behind DC/PhysOpt, and it's having problems
proving equivalence with some of DC/PhysOpt's newer optimisations.
- [ An Anon Engineer ]
Formality.
- Samuel Irlapati of Unisys
Verplex. Far ahead for years, and still far ahead despite Synopsys
efforts. Does anyone use Mentor FormalPro ???
- [ An Anon Engineer ]
We are using Synopsys Formality.
- Wilhelm Kruger of SOC Technology GmbH
I don't use EC tools.
- George Gorman of LSI Logic
We mainly use Cadence Verplex. Formality is still behind in term
of performance and debug capabilities.
- Olivier Haller of STmicroelectronics
Who's ahead? Synopsys Formality
Who's behind? Prover eCheck
- Suresh Rajgopal of STmicroelectronics
Verplex and sometimes Formality. Verplex is ahead.
- [ An Anon Engineer ]
Use an internally developed equivalence checker.
- [ An Anon Engineer ]
Cadence Verplex
- [ An Anon Engineer ]
We have used Verplex in the past, but are currently using Formality.
There seem to be some nice hooks between DC and Formality which
make the formal verification process easier (svf files).
- K.C. Buckenmaier of Hifn, Inc.
Verplex.
- Harish Bharadwaj of LSI Logic
At my last company, Verplex found a Synopsys DC bug. It was in the
newly implemented "generate" features introduced from VHDL into
Verilog 200x.
- Jeff Koehler of Ammasso, Inc.
We started with Formality, but ended up using Verplex due to problems
with Formality. Cadence is in the lead with Verplex.
- Kea Hunt of Nazomi Communications
Verplex LEC. Synopsys Formality can't deal with complex code.
- [ Kenny from Southpark ]
We use Synopsys Formality.
- Juan Carlos Diaz of Agere Systems
None.
- [ An Anon Engineer ]
Using Verplex. Earlier evaluation of Formality was not satisfactory.
Verplex has problems with some logic structures which we have to
black box at the chip level.
- [ An Anon Engineer ]
Formality. It is pretty good. Also used Verisity until Cadence
bought it.
- Michiel Vandenbroek of China Core Technology Ltd.
Cadence Verplex
- Karthik Kandasamy of Wipro
Synopsys Formality
- Ba Nguyen of SonoSite, Inc.
Synopsys Formality. We have not evaluated these tools for a number
of years as were happy with Synopsys.
- [ An Anon Engineer ]
Verplex.
- Niels Reimer of Agilent
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