( DVcon 07 Item 2 ) --------------------------------------------- [ 04/24/07 ]
Subject: Verilog vs. VHDL
A CLEARER PICTURE -- With 818 responses, this time around I was able to snag
a crisper view of the Verilog vs. VHDL world. Here's the older data:
2005 - "Does your project do mixed Verilog/VHDL simulations?"
Verilog only : ############################## 59%
mixed : ################### 38%
VHDL only : # 3%
Now here's the 2007 data with the break out of that vague "mixed" term:
2007 - "Does your project do mixed Verilog/VHDL simulations?"
Verilog only : ############################ 55.3%
mostly Verilog : ######### 18.0%
both equally : ### 6.5%
mostly VHDL : ######## 16.4%
VHDL only : ## 4.0%
The VHDL stalwarts were mostly US military contractor companies plus some
(not all, but some) European companies -- with the rest of the world being
Verilog oriented. The biggest reason why there were VHDL stalwarts were due
to legacy code reasons.
In fact "legacy" seems to be the biggest reason why Mentor Modelsim makes
its sales! Here's the grep of the word "legacy" on the user comments below.
Notice how often the words "ModelSim" or "Mentor" come up with "legacy"!
Mentor ModelSim. We do mixed Verilog/VHDL simulations due to
legacy code.
ModelSim, mixed language: internal legacy IP is VHDL, bought IP
mostly Verilog, designer familiarity/preference for new code varies.
Cadence NC-Sim
Yes - for legacy / reuse reasons test benches were often in vhdl,
design code in verilog.
Mentor ModelSim and Synopsys VCS (soon to be exclusively VCS)
Yes, we use mixed because of legacy VHDL and the oldtimers only
want to use VHDL.
Synopsys VCS-MX
Yes, we mixed Verilog and VHDL because of Verilog IPs and legacy
in-house VHDL code.
Mentor - ModelSim/Questasim. Yes to mixed Verilog/VHDL simulations
due to 3rd party IP and legacy code.
Cadence. NC-Sim/NC-Verilog. Yes, all new code is Verilog, but
there is some legacy VHDL.
ModelSim, NC Verilog.
Mixed, often we do legacy code. My current project it Verilog only.
Legacy VHDL modules we synthesize and use a GTECH Verilog netlist
as "source".
VCS and ModelSim. Mostly verilog. Some mixed verilog/VHDL to
simulate some legacy blocks targeted at the FPGA.
ModelSim verilog from Mentor. Yes, there are some legacy VHDL codes.
ncsim from Cadence. Yes because of legacy VHDL designs.
We use Mentor's ModelSim for mixed Verilog/VHDL simulations, because
of legacy code.
Mentor ModelSim, Cadence NC-Sim
Yes, due to European company legacy is in VHDL, started to migrated
to Verilog, purchased IP is in Verilog
Mostly Synopsys VCS. However we do have an extra license of Cadence
NC-Verilog for legacy reasons.
Cadence; using mixed simulations due to legacy code and external
IPs/company buy-ins
Cadence NC. Mixed legacy code.
Synopsys VCS. Yes mixed, from some VHDL dead-enders & legacy code.
VCS and NC-SIM for both verilog and vhdl. We do mixed verilog-vhdl.
We have 3rd party IP, and some legacy IP, in vhdl. Otherwise we are
primarily verilog.
Synopsys VCS-MX
Yes, we do mixed VHDL/Verilog. We have legacy VHDL code plus we have
some Verilog cores and netlists. Some Testbenches are in VHDL.
Synopsys VCS-MX VHDL/Verilog
Integrating legacy VHDL IP into mainly Verilog environment
Mixed 50/50 split VHDL/Verilog. Gate level sims in Verilog usually.
RTL is all one or the other, sometimes mixed if using legacy IP.
Mentor's ModelSim & Questa - VHDL, System Verilog, SystemC
Yes, VHDL & System Verilog. I do it to show that we can preserve
our VHDL legacy code while transitioning to System Verilog.
We use both equally (VHDL and verilog for design)
Mentor Questasim, System Verilog for verification infrastructure.
We use mixed verilog/VHDL simulation 'always' at top level as we
have legacy code in VHDL, VHDL designers writing new VHDL code,
and verilog code from 3rd party IP vendors.
Verilog. We changed from VHDL just 6 months ago. Only legacy code
is still in VHDL. We use ModelSim.
Mostly verilog. (synopsys and cadence, vcs, nc and verilog and e)
Our legacy designs in VHDL.
Verilog. We still have pieces of *legacy* vhdl stuff we've still
not replaced.
Multiple projects. All mixed. Mostly VHDL for in-house stuff,
verilog for acquired IP, legacy, library components and GTL.
Mostly VHDL, ModelSim -- legacy IPs are in both languages.
Mostly Verilog - though more legacy VHDL keeps sneaking in.
- Mentor ModelSim/Questa - for mixed-HDL.
- Synopsys VCS-MX - for Mixed-HDL (yikes!)
Always run mixed-HDL. Made excellent progress to move to all Verilog
in the past. Now... legacy VHDL & 3rd party VHDL has deterred progress,
so we're more mixed-HDL again. :-(
QuestaSim simulator provided by Mentor. The design is mixed, due to:
1. Mixed old legacy staff with new developed design.
2. Modules which was ordered from 3rd party which were written on VHDL.
VCS and ModelSim. Yes, Some legacy codes are here.
Mentor's ModelSim. Mixed-lang. There are lot of VHDL legacy blocks.
Synopsys DVE. Yes, mixed, because we still have legacy designs in
VHDL.
VHDL and Verilog, currently in ModelSim, trend is toward VCS. Yes
on mixed, mostly because of legacy VHDL code.
Mentor ModelSim. mostly VHDL. Legacy or IP/VIP.
---- ---- ---- ---- ---- ---- ----
Editor's Note: Please read the user comments in the next section to get
more on what people are saying on the Verilog vs. VHDL question. - John
Index
Next->Item
|
|
