( DVcon 07 Item 3 ) --------------------------------------------- [ 04/24/07 ]
Subject: Cadence NC-Sim, Synopsys VCS, Mentor ModelSim, Aldec
CADENCE SLIPPED? -- I'm a bit suprized this year, with Mike Fister everywhere
promoting Cadence to Wall Street and anyone who will listen, I thought they'd
do well this year. But they didn't. (And with 818 responses to this census,
it'll be fun how the Cadence sales guys will be downplaying this survey even
though my technique mimics how Cadence does their own internal surveys.)
Anyway, here's the older 2005 mindshare data:
2005 - "Whose Verilog or VHDL simulator(s) do you currenty use?"
Cadence NC-Sim : ########################### 27%
NC-Verilog : ##################### 21%
Verilog-XL : ## 2%
NC-VHDL : # 1%
Synopsys VCS : ########################################### 43%
VCS-MX : #### 4%
Mentor ModelSim : ################################### 35%
Aldec : ### 3%
Icarus : .5%
Veriwell : .5%
SimuCAD Silos-III : .5%
Finsim : .5%
Here's the new 2007 mindshare data:
2007 - "Whose Verilog or VHDL simulator(s) do you currenty use?"
Cadence NC-Sim : ######################## 24.3%
NC-Verilog : ################## 18.0%
Verilog-XL : # 0.7%
NC-VHDL : # 1.1%
Synopsys VCS : ############################################# 44.7%
VCS-MX : ######### 8.5%
Mentor ModelSim : ################################### 35.3%
Aldec : ### 2.8%
Icarus : .4%
Veripool Verilator : # .6%
SimuCAD Silos-III : 0%
Finsim : 0%
For 2007, Cadence came in second with a 24.3 + 18 + 0.7 + 1.1 = 44.1% total
Verilog/VHDL mindshare. Synopsys took the lead with a 44.7 + 8.5 = 53.2%
total mindshare.
And when you add up the percentages and find that it's 136.1% -- don't get
all stupid on me -- this census is measuring MINDshare (tool use) and NOT
MARKETshare (sales dollars) as I explained in beginning of this report.
The real story here is the *change* in the company totals from 2004 to 2007.
Cadence 2004 total : ############################## 51.0%
Cadence 2005 total : ############################## 51.0%
Cadence 2007 total : ########################## 44.1%
Synopsys 2004 total : #################### 34.0%
Synopsys 2005 total : ############################ 47.0%
Synopsys 2007 total : ############################### 53.2%
Mentor 2004 total : ######################### 41.0%
Mentor 2005 total : ##################### 35.0%
Mentor 2007 total : ##################### 35.3%
others 2004 total : ###### 11.0%
others 2005 total : ### 5.0%
others 2007 total : ## 3.5%
What happened? While Mentor remains pretty much the same 35%, Synopsys now
has picked up a 9.1% lead over Cadence in customer HDL simulator use! Huh?
My guess is this shift might be coming from how Synopsys (and Mentor) have
been enthusiastically pimping System Verilog; while Cadence's been somewhat
aloof and standoffish about it. But that's just a guess.
And I can't really blame Cadence for being not-so-excited-about SV, though.
When Synopsys bought Superlog years ago, it gave them an unfair head start
in the System Verilog biz. (It's the same reason that the Sony Walkman
people couldn't come up with iPods because it would hurt their Sony Records
holdings.) You really can't endorse a rival's technology initiative; it
makes you look bad and at best you're always playing catch up afterwards.
Mentor Modelsim. We do do some mixed verilog/vhdl sim's but these
are usually forced on us by IP models only being availble in
Verilog. We currently design using vhdl but are starting to think
about jumping to System Verilog.
- Jeremy Ellis of Ericsson
Synopsys VCS-MX. Mixed, because design is traditionally in VHDL,
IP sometimes in Verilog, testbench in System Verilog.
- [ An Anon Engineer ]
Cadence Incisive 80%, Synopsys VCS 15%, Synopsys VCS-MX (for VHDL
due to acquired IP) 5% currently, emphasis shifting to VCS due to
better System Verilog support.
- [ An Anon Engineer ]
Principally Synopsys VCS.
We tried to keep the code building with Cadence NC-Sim too, but there
were too many differences in scope of System Verilog support to
maintain this for the entire code base (at the time we looked - may
have improved now) - some people use NC-Sim for module test though.
- [ An Anon Engineer ]
Our group is all Verilog. We use Cadence NC Verilog. We are looking
at switching to VCS because their simulator offers more support for
System Verilog.
- [ An Anon Engineer ]
Were currently using a mixture of Synopsys VCS (for unit-level) and
Cadence Incisive (for system-level). We do run mixed simulations
because of IP coming from an internal European group which was using
VHDL at the time they were acquired.
- Kelly Larson of Analog Devices
MTI, in most of the cases mixed simulation or VHDL-only if possible.
- Andreas Dieckmann of Siemens
Synopsys VCS, No mix, verilog only
- Alex Orr of PicoChip
Synopsys VCS/VCS-MX
Mentor Modelsim
Cadence NC-Verilog
Mixed Verilog/VHDL (rarely) - VHDL RTL, System Verilog testbench
- [ An Anon Engineer ]
nc_verilog
verilog only
- [ An Anon Engineer ]
VCS
- Ambar Sarkar of Paradigm Works
VCS and ModelSim. Mostly verilog. Some mixed Verilog/VHDL to
simulate some legacy blocks targeted at the FPGA.
- Joe Barz of General Dynamics
Synopsys VCS-MX
Mixed because we have Verilog IPs and legacy in-house VHDL code
- [ An Anon Engineer ]
QUESTA for Mentor for SOC verification, NC from Cadence for IP
verification. VHDL/Verilog mix simation for SOC verification.
(IPs in Verilog/VHDL; top is VHDL)
- Thomas Goust of STMicroelectronics
CADENCE ncverilog
No mixed simulation
- [ An Anon Engineer ]
VCS. We have been Synopsys for a while.
- Dan Joyce of Hewlett-Packard
Axiom for verilog/vera. No mixed vhdl.
- Andrew Peebles of Cortina Systems
Mentor's ModelSim PE/SE. One is mixed.
Generally write in VHDL. IP is in Verilog.
- Steven Snyder of ITT
Mostly Aldec Active-HDL expert edition mixed language. I occasionally
use Modelsim PE-VHDL, but only when required by a customer, as I find
the Aldec tool easier to use and has considerably more features. Our
Aldec seat also supports mixed language, including suppport for EDIF
netlists, where my Modelsim seat is VHDL only. My IP is all VHDL, but
I do often have to integrate customer IP or models written in Verilog,
so I do fairly often deal with mixed language simulation.
- Ray Andraka of Andraka Consulting
Cadence NC-Verilog ver. 5.5. No mix.
- Jeff Bray of Analog Devices
Main simulator is Mentor Graphics Modelsim. Some validation on
Synopsys VCS and Cadence INCA.
- [ An Anon Engineer ]
We use Aldec for FPGA simulations, and VCS-MX for ASIC sims. We do
mixed verilog/vhdl simulations because we design in VHDL, but our 3rd
party IP is in Verilog or System Verilog.
- Samir Patel of Tarari
Synopsys VCS-MX. VHDL only if necessary for Vendor IP.
- [ An Anon Engineer ]
Cadence NC-Verilog (no mixed)
- Paul Davies of Cisco
VCS; mostly verilog, use some VHDL in Europe because it's mandated
- [ An Anon Engineer ]
VCS Verilog only - no mixing
- Marty Deneroff of D.E. Shaw
ModelSim, mixed language: internal legacy IP is VHDL, bought IP
mostly Verilog, designer familiarity/preference for new code varies.
- Helmut Reinig of Infineon
NC-Sim
- Michele Borgatti of UPEK
We use Mentor Graphics Modelsim. Yes we do mixed verilog/VHDL
simulation because we purchase IP that is only available in
Verilog. All of our code development is done using VHDL.
- Bruce Meyer of L-3 Communications
ncsim; cadence; mixed, because some project has inherited VHDL code
- Jin Song Liu of Agere
We use ModelSim (mostly VHDL), believe it or not. RivieraPro (Aldec).
- [ An Anon Engineer ]
We use Synopsys VCS simulator. No mix mode is used.
- Sam Bishai of Cisco
Cadence. NC-Verilog. No mixed.
- George Gorman of LSI
Cadence ncsim & Mentor modelsim
Yes mixed, we collaborate with our european design centers who use VHDL
- Greg Tumbush of AMI Semiconductor
Cadence NC-Sim. Mixed because:
a) we develop in VHDL
b) 3rd party IP is usually in Verilog
c) some tools only export Verilog behavioural models (Arithmatica)
d) gate level sims of a Verilog netlist are done on a VHDL testbench
We also have Modelsim for chasing any customer issues with our IP.
- Piers Barber of Imagination Technologies
Cadence Incisive and Verilator under OSC. This lets us have a Verilog
and SystemC environment, and be able to switch between Cadence as a
sign off simulator and the faster license-free Verilator+OSC sims.
Bias Disclosure: I maintain Verilator for SiCortex.
- Wilson Snyder of SiCortex
Icarus Verilog for short simulations, Verilator for long simulations.
- [ An Anon Engineer ]
We have VCS, NC-Verilog, & even a few ModelSim licenses hangin round.
I personally use NC-Verilog because I'm familiar with it but the
front-end guys swear VCS is faster.
Mixed: Yes, because some IP still comes in with VHDL. Go figure.
- [ An Anon Engineer ]
Synopsys VCS and Cadence NC-Verilog
- Tim Murphy of Agere
Cadence NC is our prime simulator. We have several Modelsim seats
as well. We do mixed Verilog/VHDL when required. Prefer Verilog
enormously over VHDL.
- [ An Anon Engineer ]
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