( DVcon 07 Item 5 ) --------------------------------------------- [ 04/24/07 ]
Subject: Certess Certitude
THE OTHER COVERAGE TOOL -- This is one of those "surprize" tools that popped
out of the user survey comments. It appears to be some sort of jacked up
coverage tool, but I'm not exactly sure what it is. (Read for yourself.)
Interestingly this is 1 of 2 new "coverage" tools -- check out the next part
of this report with user comments on the unnamed Nusym "DeNibulator" tool.
It's called Certess and their tool Certitude injects errors into the
DUT and runs you regression to see if you would catch it. They use
a form of coverage to find which tests cover which errors and can
optimize significantly so they do not have to run every test against
every error.
We have run Certitude against 5 block test benches and found problems
with 4 of them including 2 of the test benches where a data bus was
not being checked. One had a commented out "Error" message and the
other was overwriting bad data with good data just before checking
(a pass by reference not value issue).
There are some compatibility issues with Certitude and 0-in plus some
philosophical questions on how they interact with assertions, but we
are very pleased with the tool.
The company has been responsive to our open issues (about 15 in all,
so it's not perfect), and have probably one of the nicest user
interfaces I have ever seen in a tool. This would have to get my vote
for the coolest technology I have seen in the last couple of years.
- [ An Anon Engineer ]
We use Spyglass and code coverage with ICC.
We also use a tool named Certitude from the Certess company, which gives
much better results than code coverage in order to estimate where we
are in verification. We're in the process of replacing traditional code
coverage. You should have a look to http://www.certess.com -- one of
the worst EDA web sites, but you can still get information.
- Thomas Goust of STmicroelectronics
Linter: Cadence HAL
Code coverage: Cadence Conformal
Testbench checking: Certess Certitude
Certitude is a new class of tool, btw, not sure where to put it on your
question list. It fills what was previously a fairly large hole in most
DV methodologies.
You also didn't ask about CDC checking, which is very important on
today's multi-clock designs.
- Carey Kloss of Aquantia
Certess Certitude tool is used for RTL code coverage and verification
environment qualification. Certitude is the only tool to measure the
quality of a verification environment (tests & checkers effectiveness).
We found several RTL bugs after improving efficiency of verif platform
following the Certitude report.
- [ An Anon Engineer ]
For coverage we use line coverage from Cadence ICC and functional
coverage from specman e. We are just starting to ramp up on the
tool from Certess called Certitude. It has so far shown itself to
be useful in closing the gap between what you planned on testing
and what you should have tested.
- [ An Anon Engineer ]
We use Cadence HAL to check RTL coding and TransEDA Vnavigator for
code coverage. Since last year, I use another tool call Certitude
from Certess. This tool is now mendatory in our verification flow.
It allow us to get metrics and answer the question: how confident
could we have in our verification to release the chip and tape-out?
We can identify exactly the risk we take releasing the chip with
the verification level we have achieve.
- Xavier Jacquart of STmicroelectronics
Linter: Atrenta Spyglass
Coverage: builtin coverage tool from VCS -- CoverMeter
Though it is not coverage tool per se, there is a new tool in this
space, Certitude, which goes beyond traditional coverage tools, and
helps address verification quality/closure/issues with propagation
and detection. Part of the tool is the 'activation' phase where it
identifies if a particular line/cond is activated by your existing
testbench. Indirectly that gives your coverage numbers.
Since there is no specific question about this topic, let me cover
the tool here. It also injects errors into the design and checks if
the error is 'propagated' to the checkers and also if verification
checkers are 'detecting' the errors. So it helps one assess the
quality of their verification code. Very unique tool in that respect.
We have been using it for few months now. Though, we have not
finished a project with the tool, so far it proved to be useful.
- [ An Anon Engineer ]
Side comment - we recently evaluated Certess Certitude and had good
results. It looks for holes and give us feedback on how well we were
testing our design. What we really ended up finding out in the end
is that the tool provided a comprehensive 'checker review'. We spend
gobs of time in code reviews, but never really put the same effort
into reviewing how our checkers are written, leaving open the serious
possibility of bugs. Certess is an automated way to determine how
good a job our test environment was doing at activating and detecting
bugs in the design. Highly recommended.
- [ An Anon Engineer ]
I've had the opportunity to use a new tool from Certess called
Certitude, that doesn't fit into any of your questions. It helps to
show whether the testbench is capable of propagating and detecting
bugs in the design. Think of it as a verification tool for your
verification environment.
- Steve Pearlmutter of TwoTents Systems
We are looking at a tool called Certitude from Certess. During our
preliminary it uncovered missing checkers and missing test scenarios
in our verification environment.
- [ An Anon Engineer ]
Recently we looked at a new company Certess and their tool Certitude.
Its metrics exceeds that of coverage by identifying false positives
(executed code measured by coverage that either never propagates values
to your testbench or is not verified correctly) as well as revealing
weaknesses in your verification strategy (e.g., non-propagation of
injected faults can suggest the need for additional or more robust test
cases, which would not be obvious from coverage alone).
- [ An Anon Engineer ]
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