( DVcon 07 Item 8 ) --------------------------------------------- [ 04/24/07 ]
Subject: Cadence Verisity Specman "e" vs. Synopsys Vera
OUTSIDE INFLUENCES -- Even 2 years ago, most of the engineers knew this was
coming. It was really just a matter of exactly when the tipping point hit.
Here's the old 2005 stats for Verisity Specman "e" and Synopsys Vera use.
2005 - "What do you think about Verisity Specman 'e' vs. Synopsys
Vera? Does your project use either of these?"
don't use : ################################# 43%
Verisity Specman "e" : ###################### 29%
Synopsys Vera : ##################### 27%
we use both : # 1%
And now here's the newer 2007 stats:
2007 - "Does your project use either Cadence Verisity Specman "e" or
Synopsys Vera? (Yes/No) If yes, which one?"
don't use : ############################################ 57.1%
Verisity Specman "e" : ############## 18.2%
Synopsys Vera : ################ 20.7%
we use both : ### 3.9%
Yup, you're seeing that right. All forms of Vera and "e" use has noticeably
dropped in the past 2 years. The "don't use" responses have vividly jumped
from a 43% minority of projects in 2005 to a 57.1% majority of projects in
2007. This is the demise that was being openly talked about back in 2005.
2005 - "Where do you think specialty functional verification languages
like Specman "e" and Vera be in 5 years? (Choose one): Dead
or an ever growing part of the chip verification process?"
Dead : ####################################### 78%
Growing : ########### 22%
2007 - "Where do you think specialty functional verification languages
like Specman "e" and Vera be in 5 years? (Choose one): Dead
or an ever growing part of the chip verification process?"
Dead : ######################################### 81.7%
Growing : ######### 18.3%
From the comments, it seems System Verilog (and to a lessor degree) SystemC
use is finally now taking that long predicted bite out of Vera and "e". And
even as a shrinking minority, I did notice a number of fanatical Specman "e"
users who were still very enthusiastic about their language. Vera didn't
seem to have such fanatics -- instead, its users seemed to be OK just giving
in to the big, aggressive Synopsys/Mentor/ARM System Verilog marketing push.
We definitely use Specman-e.
E will be in use in 5 years at least because of the broad basis
of e-code and as long Cadence remains committed to e, we don't
see the necessity to shift.
- Andreas Dieckmann of Siemens
yes, e. At the time we decided, e was better. Can't tell about
today, because we don't want to change our whole bunch of testbenches
without a VERY SIGNIFICANT benefit.
As long as the alternatives do not support pragmatic aspect
orientation, but only strict object orientation, I don't
expect/hope e to die.
- Helmut Reinig of Infineon
Most projects still using Specman.
I believe that they will continue to grow. System Verilog in the
long run won't fully meet the needs of verification engineers.
- Steve Pearlmutter of TwoTents Systems
We use Vera on a very limited basis. We have largely replaced it
with VCS NTB. We do not plan to use it on any future projects as
SV capabilities meet the need.
We see no particular benefit of either E or Vera.
Dead, DEAD DEAD!!! The performance and operational simplicity (plus
beeing included free) of using the simulator's built in capabilities
with SV leave absolutely no room for these tools to exist.
- Marty Deneroff of D.E. Shaw
VIP using Vera, but we don't write any ourselves.
Hopefully dead.
- [ An Anon Engineer ]
We use Vera. I like Vera as a language much better than Specman-e.
As a tool I like Specman better. It has been 5 years since I have
used Specman though.
Dead. System Verilog will replace them. Synopsys current pricing
for Vera has prompted us to start investigating System Verilog.
- [ An Anon Engineer ]
Synopsys Vera.
Language features will be assimilated in newer languages.
The original languages will disappear.
- Ambar Sarkar of Paradigm Works
We're currently using Synopsys VERA. We have no "e" experience.
Comparing System Verilog and VERA, I'd say that SV is cleaner, but
implements/supports a lot of the VERA/RVM. I like SV better so far.
Specman "e" and "VERA" will be dead in 3 years.
- [ An Anon Engineer ]
Specman extensively. We use what we have. Don't know that it's
better than Vera.
Dead - over-run by System Verilog.
- [ An Anon Engineer ]
vera, I think "e" is a little better but only with some points.
System Verilog has been tested (with VCS), not stable enough at
this point.
I think "e" & vera awill be dead within 3 years. I think cadence
won't be able to charge $$ for "e" anymore, it will kill specman.
- [ An Anon Engineer ]
Vera; it is better than e
Merged into System Verilog or SystemC or some other standard.
- [ An Anon Engineer ]
both no
dead, standard will be System-Verilog
- [ An Anon Engineer ]
No to both.
Not dead, but not growing either. System Verilog will take over.
- [ An Anon Engineer ]
no use of either
Dead. Special languages need to be much much better than
standard languages for anyone to use them.
- [ An Anon Engineer ]
We use Vera in the form of the AHB VMT stuff. I have used Specman
in the past, to be honest none of them have something so special as
to raise them above the others in usefulness terms, they all do
pretty much what they claim in slightly different ways.
I think we'll see these and other languages still in the future
until something paradigm shifting comes along.
- Alex Orr of Picochip
No use of either.
I am not sure about "e".
I think VERA will be dead.
- [ An Anon Engineer ]
Yes, use Specman. When both have been compared in the past, Specman
won out.
They will have to share the space with System Verilog as some things
will be done in that whatever the benefits of a dedicated HLVL;
marketing people say so, and so it shall be......
- [ An Anon Engineer ]
Yes, Specman.
e will win.
- [ An Anon Engineer ]
No Specman or Vera. Expect consolidation on System Verilog.
The tools will stick around for the sake of taking money off us.
- [ An Anon Engineer ]
No use.
Dead.
- [ An Anon Engineer ]
No.
Dying. I certainly wouldn't start a new project with them.
- Wilson Snyder of SiCortex
Past projects have used "e", and a separate current project in our
lab is using "e". From our past evaluations, I would say "e" is
somewhat superior to vera.
I think e and vera will be supplanted by System Verilog.
- [ An Anon Engineer ]
Yes, Specman
Growing.
- [ An Anon Engineer ]
Yes on VERA. We like it and will move to Native Test Bench when it
is convenient - for performance.
I think VERA has already merged into System Verilog and Native Test
Bench. I expect the use of object oriented testbenches to continue
to grow slowly.
- Dan Joyce of Hewlett-Packard
Specman "e"
I bet on SV and SVA
- [ An Anon Engineer ]
No use of either.
I predict Specman dead, Vera ever growing.
- [ An Anon Engineer ]
Only Specman 'e'.
I guess it will be rowing.
- [ An Anon Engineer ]
We use Specman. We feel it is (still) the best one around.
In 5 years time, I believe System Verilog will take over.
- [ An Anon Engineer ]
Use none.
Former "e" transition to System Verilog for standard. Dead.
- [ An Anon Engineer ]
We are using Verisity Specman "e" - never used Vera so I do not
know which is better.
Not sure if they both may be dead (?)
- Paul Davies of Cisco
I use neither.
Dead. Too many other languages - SV seems to be the standard.
Why should companies want to support all the others?
- Keith Garvens of Hitachi
we are using Python instead of either Specman or Vera.
- [ An Anon Engineer ]
Yes - we currently Specman e but previously used used Vera. No clear
winner as each did the job.
In 5 years I see it still in use but may be nearing end of life.
- [ An Anon Engineer ]
No use of either Specman e nor Vera.
Dead. Moving to SVA.
- Michele Borgatti of UPEK
Use neither.
Dead. System Verilog and SystemC will become more popular.
- [ An Anon Engineer ]
No - both are too much of a pain.
Dead.
- [ An Anon Engineer ]
Our project used both. I've had no exposure to "e", so I can't
honestly say if one is better than the other.
Vera will be dead. Get a sense from our Synopsys AE's that they're
moving Vera under the hood and will focus on System Verilog.
- [ An Anon Engineer ]
No use of either.
Dead. Replaced with System Verilog.
- Kishor Mistry of Gennum
Yes, Synopsys Vera - not sure which is better.
If not dead, dying. System Verilog will be taking over this role.
- [ An Anon Engineer ]
Previously used 'e', but not any longer.
Not dead, but certainly in decline as people move to System Verilog and
SystemC.
- [ An Anon Engineer ]
Used Specman "e" on project a year ago. Liked Vera better, especially
when it was combined into VCS.
Given our experience, we expect specialty languages to go away.
- [ An Anon Engineer ]
Not currently. We used to use Vera and I found it to be OK.
My best guess is that they will be supplanted by System Verilog/SystemC.
- [ An Anon Engineer ]
Synopsys Vera. Synopsys Vera is much better.
Dead will be replaced by System Verilog. Although I should note
the System Verilog is based on Vera.
- [ An Anon Engineer ]
Don't use.
Dead. Because I think System Verilog supercedes them and will
apparently be widely supported by tools.
- [ An Anon Engineer ]
NO USE.
DEAD, complexity, cost and overhead to maintain these processes
are gong to be greater the benefit gained.
- Bruce Meyer of L-3 Communications
Don't use.
They will continue to be used. However, the use will decline as
companies shift to System Verilog.
- [ An Anon Engineer ]
None.
Dead. hopefully system verilog will take over
- Rowan Lyons of Duolog
Yes, e.
e may not be dead, but it will shrink.
- [ An Anon Engineer ]
Current project no. Previous project was using Vera (NTB actually).
I've seen e. I could not work with e, but I did enjoy NTB.
Specman "e": dead. Vera: Its legacy lives on in System Verilog.
- [ An Anon Engineer ]
Specman.
Growing.
- [ An Anon Engineer ]
Yes, we use Specman e.
Dead, because industry seems more instersted in System Verilog,
although I do not see any major improvement in SV vs. Specman e.
- Jin Song Liu of Agere
None.
Dead. The choices for high level testbenches are varied. Why choose
a proprietary language that you have to pay for a license every time
it is used? A large multi-user all SystemC development environment
is free.
- Greg Tumbush of AMI Semiconductor
No use.
Dead, movement everywhere is to System Verilog open standard.
It will be part of the basic simulator.
- [ An Anon Engineer ]
Used Synopsys Vera for years, switched to Axiom about 2 years ago.
Was involved with Specman at Cisco for a couple of years. Hated it.
They won't die, because of the built up code base within companies
and the built up knowledge base.
- Andrew Peebles of Cortina Systems
One of our 2 major projects is using Vera, and a previous project
currently in prototype used Vera. I'd say Vera is better only
because its ideas are carried over into SV Testbench.
Standalone languages like "e" and Vera will be dead, replaced
with SV (for better or worse)
- [ An Anon Engineer ]
None now. I have used both - each is better in different ways.
Dead. Replaced by System Verilog even if Cadence thinks
System Verilog is good only for block level testing.
- George Gorman of LSI
No.
Any language that isn't open and standardized will be dead!
- Jonathon Rose of ATK
Specman.
Specman "e" will last another 10 years. It is good for functional
verification due to its portability.
- [ An Anon Engineer ]
No.
Dead.
- Gautham Kamath of Cirrus Logic
None.
Dead. I think System Verilog will take over; or maybe Teal/Truss.
Have you heard of it? It's pretty new but starting to get some
momementum: http://wwww.trusster.com
- [ An Anon Engineer ]
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