( DVcon 07 Item 11 ) -------------------------------------------- [ 05/24/07 ]
Subject: SystemC
OH, CRAP! -- SystemC use dropped by 1/2 in the past 2 years! I can already
see the witch hunt where the SystemC fanatics are calling for my head.
2005 - "Do you see your project using SystemC in the next 6 months?"
yes : ##################### 42%
no : ############################# 58%
2007 - "Is your project using SystemC? (Yes/No)"
yes : ########### 23.0%
no : ####################################### 77.0%
I have no idea what went wrong here. All I know is that the slick Synopsys
Marketing weasils will say this just proves the ascendancy of their glorious
System Verilog over a SystemC that they wisely abandoned years ago. Behind
my back, the Cadence Marketing sleaze will attack me personally and call the
census "horribly biased" and "that Cooley guy is not to be trusted."
And depending on where their private vested interests lay, all the effected
smaller EDA companies will either join the Synopsys or Cadence approach on
this issue. Oh, goody. Oh, joy. Oh, crap!
I called Gary Smith about my problem and he said: "Calm down. Calm down...
What you're doing is comparing apples to oranges. You can NEVER mix surveys
of what people say they WILL do with the people saying what they ARE doing.
I've even stopped asking people what they WILL do in my own surveys, cause
those numbers are almost always wrong. Your 23% number for current SystemC
usage sounds about right from what I'm seeing. Your data's OK, John."
Whew!
Anyway, asking those in 2005 and 2007 who are using SystemC:
2005 - "Are you using SystemC for high level modeling,
or verification, or for design?"
high level modeling : ####################### 70%
verification : ##################### 62%
design : ## 7%
2007 - "Are you using SystemC for high level modeling, or for
verification, or for design? (Choose all that apply)"
high level modeling : ######################### 73.7%
verification : ###################### 64.2%
design : ## 5.8%
It's interesting how the percentages haven't changed for this particular
question over the past 2 years. It seems that despite all the actions of
the Forte Cynthesizer and Mentor Catapult C marketeers, SystemC and ANSI C
are both still seen primarily as modeling/verification languages only.
Again, asking only the actual SystemC users in 2005 and 2007:
2005 - "Whose SystemC tools are you using?"
Cadence NC-SystemC : #################################### 36%
Cadence TestBuilder : #### 4%
CoWare : ### 3%
Free OSCI : ################################# 33%
Mentor ModelSim : ################ 16%
Synopsys CoCentric : ########## 10%
Mentor Catapult C : # 1%
Forte Cynthesizer : # 1%
Synfora Pico : # 1%
2007 - "Whose specific SystemC tools are you using?"
Cadence NC-SystemC : ################################## 33.6%
Cadence TestBuilder : # 0.9%
CoWare : ####### 6.5%
Free OSCI : ########################################### 43.0%
Mentor ModelSim : ################# 16.8%
Mentor Summit Vista : ########### 11.2%
Synopsys : ################ 16.0%
Mentor Catapult C : 0%
Forte Cynthesizer : #### 3.7%%
Synfora Pico : 0%
all others combined : ##### 4.7%
If you look just at SystemC simulators (the mainstay SystemC tool), beyond
the dog slow & free OSCI simulator, Cadence easily dominates the SystemC
space with 33.6% vs. a weak Mentor ModelSim 16.8% and Synopsys 16.0%. Even
combined, Mentor & Synopsys still can't beat Cadence in the SystemC game.
4.) Is your project using SystemC? (Yes/No) If yes, are you using it
SystemC for high level modeling, or for verification, or for
design? (Choose all that apply) Whose specific SystemC tools
are you using? Give names.
No SystemC. Why do we need it? We use VHDL which was developed for
high level modeling as well as RTL and gate-level design. However,
VHDL is a very poor netlist language. We use Verilog for netlists.
Yes, we have written 650 K lines of SystemC/C++ to verify a chipset
with 3 chips. We use the SCV library and Cadence Verification
Extensions as our verification language, and have developed an
internal methodology similar in concept to the vendor's AVM, eRM,
VMM. We don't use SystemC for design, only for verification.
We are using SystemC for verification. Use NC-SystemC that comes
with Cadence Incisive.
Yes. Verification. Cadence NC-SystemC.
No, no usage of SystemC
Yes. For modeling & verification. No tools except Emacs. ;-)
No we don't use SystemC.
Yes. We have used SystemC for platform level modeling.
The tools were from CoWare.
Yes, high level modeling and verification. Cadence.
Not using SystemC yet, but plan to for modelling.
Yes. Complete testbench SystemC. Complete IP cores SystemC.
Behavioural and RTL style. Some protocol adaptors in Verilog/VHDL,
DFT stuff Verilog. Forte as tool.
Currently doing proof of concept using CoWare.
No. We don't.
Yes for modelling, some verification and design. The tools in use
OSCI SystemC, ARM OptimoDE framework, & ARM RealView Create family
SystemC: no
We have a full inhouse verification based on SystemC Mentor Questa
No, we are using Verilog for design; Specman for verification
No SystemC
Yes, for architecture-level modelling (using homegrown add-on libs
above plain SystemC and public-domain SystemC simulator kernel).
Not for verification, nor for design.
Yes. We use SystemC for reference modeling in verification.
Using Synopsys VCS co-simulation between System Verilog and SystemC.
No, but previously for high level modeling and verification.
Cadence.
Yes, for high level modeling and for verification.
We use the public class libraries plus our own.
No. Used it for system/performance modeling on last chip, not
using it on current chip.
No. We tried writing some SystemC code 4 years ago when starting
the company. Had it running standalone OK. Then Synopsys tried
to demo their SystemC-of-the-day (CoCentric?). They failed
miserably the instant the AE loaded it into the tool and it could
only handle our code by defining it as a black box. Then we
decided that Verilog was more productive at actually producing
things called gates. We can actually sell gates.
Mostly No. When used it's for verification. Mentor Questa AFV.
Yes. Modeling and verification.
Using the Verilog/SystemC interface in VCS.
Yes, verification. Modelsim.
No, but we have started designs with Handel-C from Celoxica.
No SysC. If I did, it'd be for architectural sims only.
Yes. We use it mostly for verification but there is some high-level
modeling in use by some teams. We use the OSCI source code compiled
into our hardware development kit. At this point, I don't think we
have relied on any native SystemC implementations in the tools.
Yes - high level modeling PV, same model used for early SW
development, IP verification expected datas. Designers are using
C based synthesis (not SystemC specific) and OSCI simulator and
Cadence NC-SystemC simulator.
No. I've used SystemC for high level modelling in my last project
(which ended up getting cancelled). My current project does
not use high level models.
No, although we expect RivieraPro to be able to handle SystemC
eventually.
No - while my designs are SOC, they are very small by today's
standards so I don't see the need.
Yes it's used for verification (not heavily). Cadence NC-SC used.
We have one project that used SystemC. Yes. Only high level
modeling. We used the Synopsys one. We only simulated, never
synthesized it.
No, I never used it, is it dead?
No. We do use C for high level modeling, but not SystemC.
Yes - for architectural modeling.
Pure OSCI, no interfacing with VCS.
No. I've tried SystemC for verification once and soon threw it
out again because it was insanely slow. (Profiling showed it
was spending 80% CPU time in handling the template code that is
implementing the bitstrings/vectors.) Haven't looked at SystemC
again in a while. That was with the free OSCI SystemC simulator.
Currently we only use Verilog.
Yes, high level modeling, verification using Mentor ModelSim.
No, used objects in the past.
No on SystemC.
Yes - for verification. We use Aldec SystemC (Synopsys sucks).
Not applicable. Do not use.
Yes. High level modeling. Concept Engineering GmbH.
Yes, our entire Verification framework is SystemC.
Cadence Incisive, OSCI, and System Perl on top of both.
No and we have no plans to.
Yes, Cadence SystemC support. We primarily use this for a dynamic
MEM model. Some architectural exploration is done using SystemC.
Yes, modeling, verif. Cadence for now. Just beginning to use...
Next project we are looking at this.
Yes. High level modelling. ARM SoC designer.
No, although we do use SystemC type families for C simulation.
No SystemC. We looked into Carbon tools which is very promising but
didn't decide to buy due to budget constraints.
No SystemC on this project.
We are using SystemC for the next project. I think the team is using
Open Source OSCI tools mostly but also use the Summit design tool.
Visual Elite for high level modeling
All of our new development in SystemC is all high level modeling.
We have some legacy SystemC for verification, all new development
is System Verilog. Cadence & Synopsys both allow very easy
integration of SystemC into Verilog, that's worked well.
No SysC. Has been talk for long time about possible use, but it's
still all talk.
We are not using SystemC.
Planning to use it for future verification reference models. Might
think of using it for HL modeling as well.
No. There are trials in another site, have not yielded anything
yet. SystemC has potential making our site look better by our
not wasting time on it. ;-)
Current project does not use SystemC.
We have been using SystemC for high level modeling for close to
5 years now. We are now using SystemC for cycle accurate models
used for verification. Have not plans to use it for design. Most
development is done with the OSCI kernel only. Have used Summit
to help in debug. Verification work makes use of SystemC cosim
capabilities of Cadence IUS and Mentor Modelsim.
SystemC = No
We use one of its ancestors, Testbuilder. We have our own C++
classes layered over it. We use it for high level modeling, as
well as verification.
Yes. HLM and verification. We use OSCI.
Not yet. We are waiting for a customer to request SystemC.
Yes. Only for high level modeling. Freeby OSCI.
No, we tend to be more "hardware centric" we don't have the
resources to devote whole teams of "systems designers" to
support SystemC.
No SystemC is used here.
No, not yet. But I am attending some vendor presentations for
SystemC tools. We would use it for high level modeling and
some verification.
Yes, OSCI, OCP, ModelSim for TLM (BFM transactors).
Yes. SystemC library from systemc.org.
Transaction-accurate verification model.
No, we use plain ol' C/C++ for some modeling purposes, and
Specman for control.
SystemC? Yuck.
Not yet.
SystemC - NO
We use SystemC mainly to do modeling (virtual prototypes) for early
software development and architecture exploration. In this case,
GNU gcc with OSCI (Open SystemC Initiative) library is enough.
Cadence NC-Sim can also be used specially when doing co-simulation
with Verilog/VHDL. We have also started activities around behavioral
synthesis using Forte.
Yes, for high level modeling. Using with Axiom MPSIM.
Yes! Verification only. Not using any SystemC tools. Resentment
against SystemC seems to be growing among the other groups.
No.... but am planning to move to it.
Yes. SystemC is used for high level modeling and for verification
by checking the high level model against the RTL implementation
Tools: Synopsys SystemStudio, Cadence NC-SystemC, Specman, inhouse
Not at the moment, but could be used for verification. Tools and
language are not determined, but probably would use the SystemC
support of Mentor ModelSim.
Yes, high level model, high level verification (virtual prototype)
SNPS CoCentric, VAST, Mentor SystemC extension to ModelSim.
We used to use SystemC when the company started. It was used solely
to interface to our reference model which was run concurrently with
the RTL for verification. We replaced all SystemC w/ System Verilog
DPI once Cadence implemented enough of the standard in NC-Verilog.
I measured a 10% performance gain as a result of this. We will not
go back to SystemC unless we have to bring back a legacy project or
we decide to start doing this co-simulation business.
No, our project does not use SystemC.
Yes. High-level modeling, verif and design. Forte Cynthesizer.
Yes. We use it for verification. However, we are in the process
of replacing it with System Verilog. The SystemC tool we use comes
from Cadence NC.
No. Does anybody use SystemC? ;)
No. Some C models, but non-SystemC.
No, but some would like to use it for design if it was synthesized
better and supported fully by the tools.
No, but I took a class. The constructs seem to involve too much
overhead to be efficient, especially when you're an old-school
text-editor type person like myself. I'd much prefer to use SV
for all of the above.
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