( Post 43 ITEM # 1 ) --------------------------------------------------

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     SYNOPSYS BUG ALERT   SYNOPSYS BUG ALERT  SYNOPSYS BUG ALERT
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There's a bug involving PAD pins on I/O macros with Synopsys Design Compilers
(Rev. 2.2a-6762 and Rev. 2.2b).  What happens is that the compiler connects
internal wires to the PAD side of these macros.

An example:

 (BEFORE compiling)

                                             ------- random_logic_1
                                             |
                     |\   internal_signal    |
  external_signal ---| >---------------------|------ random_logic_2
                     |/                      |
                 I/O Buffer                  |------ random_logic_3
                                             |
                                             ------- random_logic_4



 (AFTER compiling)


                   --------------------------------- random_logic_1
                   |                         |
                   | |\   internal_signal    |
  external_signal ---| >-------------.       |------ random_logic_2
                     |/              |       |
                  I/O Buffer         |       ------ random_logic_3
                                     |
                                     ------- random_logic_4



Synopsys knows of this bug and says it'll be fixed when release 3.0 comes
out.


WORKAROUND UNTIL THEN:

   Place a "dont_touch" on each external_signal and the Design Compiler
   won't connect anything to that side of the I/O macro that's not
   already connected.

   (Important Note: do NOT use the "dont_touch_network" command because
    that effectively puts a "dont_touch" attribute on the transitive
    fanout of every object it finds following through a design until it 
    hits a memory element!)


( Post 43 Item # 2 ) --------------------------------------------------

  I just heard from someone who attended the recent DAC in California
  that Synopsys and Cadence has booths right next to each other.

  (Evidently, there are quite a few comparitive shoppers out there;
   because my source said that he seemed to notice that the people
   were wearing the carpet thin walking between both exhibits!)

  One odd thing was noticed by this source.  Apparently, Cadence's
  synthisizer does not appear to have a timing analyzer in it.  Therefore,
  the user has to run the compiler, get out of it and then go into
  Veritime to actually verify the design's timing.

  Can anyone confirm or deny this?		-John


( Post 43 Item # 3 ) --------------------------------------------------

  The June 8th issue of EE Times is brimming with all sorts of articles
  concerning products from various Design Automation software houses.