Editor's Note: This post is six slightly different approaches to solving the
  Scripts Bombing/Queuing problem.  Rather than choose the one or two I
  thought were optimal, I thought it would be better to let the reader himself
  choose.  Keep on sending those user tips!
                                                 -John Cooley
                                                  ESNUG Moderator

( Post 121 Item 1 ) --------------------------------------------------------

>Subject: (Post 120 Item 5) FPGA Licensing and Scripts Bombing
>
>Is there any easy way to submit script jobs once licenses are free?
>Basically we have 4 users fighting over 2 licenses and it would be
>nice to have the job that gets refused to keep trying if it couldn't
>get the licence when it tried for it.  In particular, we are fighting
>over FPGA licenses, so there is the added condition that initially
>invoking dc_shell grabs a design_compiler license, which we don't want,
>and then the script blows up since it may not be able to get a FPGA
>license.
>
>Does anyone have a script that monitors the licenses and then jumps
>in and tries? Or is there a better way?

                  --- --- --- --- --- --- ---

From: jefff@mars.sps.mot.com (Jeff Freeman)

In a bourne shell, this is what I do:

#! /bin/sh

#In a bourne shell, this is what I do:
#It will retry until it gets the license and then it will 
#run script.dc
#
# It spawns a subshell to get the license and run the process.
# If there is not license available then it waits and retries.
# Read the man page on bourne shell for more info.

EX="dc_shell -f script.dc"
LICENSE="FPGA-Compiler"

until ($EX -checkout $LICENSE) \
do { stat=$?; if test $stat -gt 127; then /bin/echo "Waiting for license..."; \
     sleep 20; else /bin/echo "Exit($stat)"; exit $stat; fi; } done

  - Jeff Freeman, Motorola

                  --- --- --- --- --- --- ---

From: hill@pau.synnet.COM (Shannon Hill)

We use nqs-2.2 (a fairly fancy batch queueing system, available at many
internet sites) to set up queues so that no jobs ever fail to run because
of license exhaustion.  It's a shame that Synopsys doesn't support some
sort of "try to get this license, if fail, wait, try again" construct in
dc_shell; though I expect they have a business interest in not supplying
users with this handy feature

  - Shannon Hill, hill@synnet.com

                  --- --- --- --- --- --- ---

From: Greg Brookshire

We had this same problem with all of our licenses.  We had our system
administrator write a queuing script which allows many users to submit
jobs for the evening.

We also use scripts like this one, which waits for a Design-Compiler
license to come free.  It executes the lmstat command every 30 seconds
until there are less than 6 licenses in use.  Just call this script
before you call dc_shell.

#!/usr/local/bin/perl
#
# This perl script waits for a Synopsys licenses
#
$num_design_comp = 6;  ### total number of licenses
$partname = '';

while( $num_design_comp >= 6) {
   $num_design_comp = 0;
   open(output,"lmstat -A -c /usr/synopsys/admin/license/key |");
   while (<output>) {
      if (/Design-Compiler/) {
         $partname = "design";
      }
      if (/started/) {
         if ($partname eq "design") {
            $num_design_comp++;
         }
      }
   }
   if ($num_design_comp >=6) {
      sleep(30);
   }
   close(output);
}
----- end of script

This script parses output which looks like this:

lmstat - Copyright (C) 1989, 1990, Highland Software, Inc.
Flexible License Manager status on Fri 4/93 8:37

License server status:

     brave: license server UP (MASTER)
     tribe: license server UP
     chief: license server UP

Vendor daemon status (on brave):
 
 synopsysd: UP

Feature usage info:
 
    Users of LSI-Interface:  (1 licenses available)
    Users of Test-Compiler:  (2 licenses available)
    Users of Design-Analyzer:  (7 licenses available)
    Users of Design-Compiler:  (4 licenses available)
    tviola at cherokee on /dev/ttyp5 (v2.200), started Fri 4/93 at 8:18
    Users of VHDL-Compiler:  (4 licenses available)
    Users of DC-Expert:  (4 licenses available)
    Users of DC-SDF-Interface:  (4 licenses available)
    Users of SynLib-Eval:  (8 licenses available)


Hopefully you have a similar report from your license manager.

Good Luck!

Greg Brookshire

p.s.  We used to have 25 people fighting for 4 Design Compiler licenses!

                  --- --- --- --- --- --- ---

From: d_pinvidic@emulex.com (Dan Pinvidic)

In order to share our HDL Compiler license we use the following 
dc_shell commands in our compile script to loop until the license is
available.  If the license is not available, a Unix sleep command is
executed for 60 seconds before retrying.  After 5 minutes we exit.

If you are sharing the Design Compiler license you can insert a test of
$status (This is the return status after calling dc_shell).  It will
be 0 for normal completion and NON-ZERO if the command failed ie. no
license.

  - Dan Pinvidic
    Emulex Corp.

vfile = verilog_source_file

/* Start of read function  */
TIME_OUT_CNTR = 5
while (TIME_OUT_CNTR != 0)
 {
   read -format verilog vfile + ".v"
   if (dc_shell_status == "{}" ){
         echo "Unable to read file, waiting to re-try"
         sh sleep 60
 
         TIME_OUT_CNTR = (TIME_OUT_CNTR - 1)
         echo "TIME_OUT_CNTR = " TIME_OUT_CNTR
         if (TIME_OUT_CNTR == 0) { echo "Giving UP......." ; }

    } else { remove_license HDL-Compiler;break; }

  }

if (TIME_OUT_CNTR == 0) { quit ; }

/*  End of read function  */

                  --- --- --- --- --- --- ---

From: jmuha@sedona.intel.com (James Muha~)

John,

Here is a script we use to monitor licenses and jump in when they are
free.  It checks for Design-Compiler and VHDL-Compiler and could easily
be modified to check for an FPGA license.

  - James Muha~
    Intel Corp.

#!/bin/csh -f

set key_file = `cat $SYNOPSYS/admin/license/key`
while ($#key_file > 0)
    if ($key_file[1] == "Design-Compiler") then
        shift key_file
        shift key_file
        shift key_file
        shift key_file
        set max_dc_count = $key_file[1]
    else if ($key_file[1] == "VHDL-Compiler") then
        shift key_file
        shift key_file
        shift key_file
        shift key_file
        set max_vc_count = $key_file[1]
    endif
    shift key_file
end

set dc_count = 0
set vc_count = 0

while (1)
    set var = `synopsys_users`
    while ($#var > 0)
	if ( ($var[1] == "Design-Compiler") ||
             ($var[1] == "Design-Compiler,") ) then
            @ dc_count = $dc_count + 1
        endif
	if ( ($var[1] == "VHDL-Compiler") ||
             ($var[1] == "VHDL-Compiler,") ) then
            @ vc_count = $vc_count + 1
        endif
	shift var
    end
    if ($dc_count >= $max_dc_count) then
	echo "Too many users of Design-Compiler - Will try again in 1 minute"
	sleep 60
    else if ($vc_count >= $max_vc_count) then
        echo "Too many users of VHDL-Compiler - Will try again in 1 minute"
        sleep 60
    else
	echo "Design-Compiler and VHDL-Compiler are available to you."
	dc_shell $argv
	exit 0
    endif
end

                  --- --- --- --- --- --- ---

From: danw@wellfleet.com (Dan Westerberg)

You might want to try some queueing software to solve your problem. We use
a package called the Multi-Device Queueing System which was originally 
written to handle the queueing of print jobs. However, it's vastly more
powerful and will queue virtually anything via the provided "shell server"
device.

For example, if you have 5 designers trying to access 3 licenses, you could
set up a single "synopsys" queue that is serviced by three shell server
devices, each of which represents a license. Jobs submitted to this queue
would be started on the next available device, i.e. license.

The software is easy to configure and is very flexible. It's available from
gatekeeper.dec.com via anonymous ftp as : /pub/net/applic/mdqs.2-16.tar.Z

Hope this helps,

  - Dan Westerberg
    Wellfleet Communications


( Post 121 Networking Section ) --------------------------------------------

HDL Systems is looking for several experienced Verilog and Synopsys users to
design large complex ASIC cores. FAX Brad @(408) 451-0323 E-Mail brad@hdls.COM


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