Editor's Note: Usually *I'm* the one who tells the stories. So I have
to admit it's unnerving to see what others got right and what they got
wrong when they write about me. See http://tinyURL.com/CooleyMissing.
A taste of my own medicine! Yikes! (I must tip my hat to Queen Peggy.)
- John Cooley
DeepChip.com
( ESNUG 480 Subjects ) ------------------------------------------ [04/02/09]
Item 1: Problems @ Veritools? Esterel? SiNavigator? Certess? Jasper?
Item 2: ( ESNUG 479 #4 ) Synfora PICO vs. CatapultC/Cynthesizer/CtoSilicon
Item 3: AtopTech, Magma, Apache vs. the Synopsys/Cadence package deals
Item 4: TSMC user confirms Magma Titan takes mins vs. weeks for 2nd design
Item 5: ( ESNUG 479 #4 ) A user's first look at Cadence C-to-Silicon
Item 6: ( ESNUG 477 #3 ) A hesitant RTL designer trys out CatapultC design
Item 7: Do you know of any non-Cadence-controlled OpenAccess forums?
Item 8: "Positioning" consultant says Rajeev wants to sell to Cadence
Item 9: Engineer finds PrimeTime dmsa_fix_hold works but with caveats
Item 10: ( ESNUG 477 #10 ) "Working with Bluespec is faster than with RTL"
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Trying to figure out a Synopsys bug? Want to hear how 24,298 other users
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!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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