!!!     "It's not a BUG,                            
  /o o\  /  it's a FEATURE!"                                 (508) 429-4357
 (  >  )
  \ - /              The DVcon'05 Verification Census
  _] [_                           -or-
          A Census of 338 Engineers on Design Verification Tool Use

                             by John Cooley

     "In 5 years Cadence will have killed 'e', either on purpose or by
      running the Verisity tools and support into the ground."

          - Michiel Vandenbroek of China Core Technology Ltd.

     "We use Synopsys Formality because we need to verify our Synopsys
      DesignWare implementations.  Sometimes, though, it feels like we're
      hiring Enron to be our independent auditor."

          - Tom Mannos of Sandia National Labs

( DVcon 05 Subjects ) ------------------------------------------- [ 10/25/05 ]

 Item  1: Mindshare vs. Marketshare
 Item  2: Cadence NC-Sim, Synopsys VCS, Mentor ModelSim, Aldec
 Item  3: SystemC
 Item  4: System Verilog
 Item  5: Verisity Specman "e", Synopsys Vera, SystemC SCV, JEDA
 Item  6: the Future of Specman "e" and Vera
 Item  7: IBM Sugar/PSL, 0-In CheckerWare, Verplex OVL, System Verilog SVA
 Item  8: Cadence HAL, Synopsys Leda, Atrenta Spyglass, 0-In CheckList
 Item  9: TransEDA vNavigator, Cadence HDLScore, Synopsys CoverMeter
 Item 10: Novas Debussy & Verdi, Veritools UnderTow
 Item 11: Mentor HDL Designer (Renoir), Summit Visual Elite
 Item 12: Cadence Verplex, Synopsys Formality, Mentor FormalPro
 Item 13: 0-In, Jasper, Synopsys Magellan, Real Intent Verix, Averant, @HDL
 Item 14: Calypto SLEC
 Item 15: Cadence Palladium, Verisity Axis, Mentor IKOS/VStation/Celaro
 Item 16: Mentor Seamless, CoWare ConvergenSC, Synopsys System Studio
 Item 17: Synopsys PCI, Verisity AMBA, Denali DDR, nSys PCI, ARM


============================================================================
 Trying to figure out a Synopsys bug?  Want to hear how 21,788 other users
    dealt with it?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
     !!!     "It's not a BUG,               
    /o o\  /  it's a FEATURE!"                 (508) 429-4357
   (  >  )
    \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
    _] [_         Verilog, VHDL and numerous Design Methodologies.

    Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
  Legal Disclaimer: "As always, anything said here is only opinion."
 The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com




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   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)