From: Chris Wilson <chris=user domain=nusym got calm>

Hi, John,

I'm not dumb enough to think the EDA world will change because I've written
this, but it sure would feel good just to vent about it somewhere.

There are 10x the number of SW developers (~200K) as there are HW developers
(~20K) and the software development industry is more mature.  We could learn
a lot about efficient language design from them.

Roughly 35 years ago, there were two languages vying for position as the big
second generation programming language: PL/1 and C.  IBM was the dominant
player in programming languages and was clearly in a position to have PL/1
become the de facto standard.  PL/1 was fundamentally a *superset* of the
existing mainstream programming languages: FORTRAN, ALGOL, and COBOL.

Meanwhile, Bell Labs was developing C with a philosophy 180 degrees opposite
to that of PL/1 -- C was the *minimum common subset* of existing languages,
instead of a superset.  With C, it was easy to create libraries to make up
for the lack of features found in other languages.

Essentially, C is not a language for writing programs, it is a language for
writing libraries.  Applications are built by putting libraries together.
In fact, it is not possible to write a "Hello World" program in C without
using a library (stdio).  Today, all modern programming languages still
follow this basic *minimum common subset* philosophy.

The software industry would not be as nearly as advanced today had PL/1 had
won the language wars.  The entire Open Source movement was enabled by the
philosophy behind C.  Imagine if PL/1 had won the language race and the only
way to add new standard features was to add them to the language.  The PL/1
compiler was controlled by IBM and the language was not designed to be
easily compilable.

Compare this with how hardware design languages have evolved.  Verilog and
VHDL are the hardware analogs of FORTRAN, ALGOL and COBOL.  These first
generation hardware description languages developed about 20 years ago.
Shortly after that, specialized verification languages, such as Specman "e"
and Vera, were introduced that added features useful for verification.
Then, along came assertion languages such as PSL and SVA.  Today, we are
migrating to System Verilog.

Guess which path System Verilog took?  Yup, the PL/1 path!  System Verilog
is a superset of Verilog, Vera, and SVA.  The initial release version was
version 3.1a.  That's right, it took three major revisions to get it right,
and then someone decided to add some functionality to get version 3.1.  Oh,
but wait, that still wasn't enough, we just had to have a few extra features
to get to 3.1a.

And it gets worse. 

In 35 years, there has been exactly one revision of the C language, while
System Verilog is due for a rev next year after only 5 years.  The original
Verilog has undergone 4 major revisions in 20 years.  Specman "e" and Vera,
are changed practically every quarter.

The cost of all this is that it is much harder to innovate in hardware
design than it is in software design.  I would bet that $50 million is spent
over the last 3 years on hardware *language* issues alone -- all money that
could instead have been spent moving the verification technology forward
dramatically.

At Nusym, we spend 90% of our effort (and money) on language support vs. our
core differentiating algorithms.  We've spent literally 10's of man-YEARS
developing Verilog and Vera infrastructure for our tool.  In contrast, it
took one engineer only 3 MONTHS to prototype our core tool.  

This is just stupid.

There.  I feel better now after having vented.  I'd like to write more about
this issue, but I have to get back to work making sure our tool complies
correctly with yet another XYZ standard...

  - Chris Wilson
    Nusym, Inc.                                   Los Gatos, CA


  [ Editor's Note: Chris is the CTO of Nusym and has 20 years experience
    doing HW design plus a PhD from Stanford in verification.  - John ]