Subject: Dan Nenni on climbing wafer counts yet EDA revenue stalling

>  1.) What are your 2 or 3 biggest burning EDA/design/business/tech
>      issues that you're facing over the next 3 months?  (The more
>      details you can give, the better.)


From: Dan Nenni <daniel.nenni=user domain=baesales got calm>

Hi, John,

While semiconductor wafer count is climbing, an estimated 20 M in 2009 to
30 M in 2013, EDA will continue to stagnate.

The main reason for the disjointed wafer count increase and EDA revenue
stalling is FPGAs.  As programmable devices advance in speed and density,
medium-to-small volume projects and emerging technology companies will
continue to leverage the low barrier to entry of FPGAs.  Wafer count climbs
from FPGA vendors such as Xilinx, Altera, and Actel, while ASIC design
starts decline.

Other reasons for the ASIC design start decline include:

   - High cost, it takes $50-70 M to get an ASIC to market.

   - Increased SOC design density and complexity, the chips are bigger
     so there are less of them and require more engineers to complete.

   - High chip mortality rate, an estimated 50% of the ASIC design
     starts do not make it into production.

   - Less ASIC design starts equals less design experience, less design
     experience equals higher ASIC mortality rate.

The bottom line is that to increase ASIC design starts we must decrease the
barrier to entry, we must reduce risk, we ALL must focus on "success based"
business models:

   - Foundries are certainly "success based" with wafer pricing but must
     look at reducing NRE (mask costs) which are in the millions of dollars.

   - IP companies are "success based" with foundry sponsored IP (free to
     customers), and royalty based IP, but there are still significant
     up-front licensing fees for leading edge products.

   - Design Services like eSilicon are definitely success based with per
     chip pricing for working silicon.

   - EDA is still in the dark ages with yearly subscriptions or all-you-can
     eat product dump pricing where you pay whether you use it or not,
     whether you are successful or not.  (Imagine if the FPGA market was
     NOT "success based" with $1M+ design tools and up-front licensed IP?)

If EDA does NOT share in silicon success, only the design services and the
FPGA companies will flourish, EDA will not.

    - Dan Nenni
      BAE Sales, Inc.                            Milpitas, CA