( ESNUG 342 Item 7 ) --------------------------------------------- [2/03/00]
Subject: ( ESNUG 341 #6 ) Users On ModelSim's Verilog/VHDL Co-Simulation
> We're thinking about using Modeltech's ModelSim to simulate a Verilog
> gate level design in a VHDL-Testbench. (We want to reuse the VHDL
> testbench we designed together with the Verilog RTL code of the design.)
> I'm interested in any user experiences with ModelSim's Verilog engine &
> their VHDL/Verilog co-simulation. How about their:
>
> - Simulation time ( especially for designs about 100k gates)?
> - Compile time ( especially for designs about 100k gates)?
> - Backannotation (again, for 100k gates)?
>
> If someone has experiences compared to Verilog-XL or Synopsys's VCS or
> Viewlogic's Fusion, it would be great. Many thanks for moderating the
> ESNUG, John.
>
> - Georg Zehentner
> HEIDENHAIN GmbH
From: Svein Haustveit <svh@networks.nera.no>
Hi, John,
I have a response to ESNUG 341 #6 -- "What's The Customer Dirt On ModelSim's
Verilog/VHDL Co-Simulation?" We found no serious dirt on our limited
ModelSim Verilog/VHDL co-simulation trial.
I have tried out ModelSim VHDL/Verilog cosimulation on a 300K design with
the same mix as Georg intend to use. (VHDL testbench and Verilog design).
I normally do all-VHDL simulations and the cosimulation worked out OK.
There is a single user interface and user operation is identical to single
language operation. As I understand it, there is no separate Verilog
simulation engine communicating with the VHDL simulator, but a single
simulator kernel handeling both languages.
I have no benchmark with other simulators, but ModelSim Verilog gatelevel
was 2X faster than ModelSim VITAL/VHDL gatelevel simulation (both with
testbench in VHDL). Compile time and SDF annotation is done in few minutes
and is not an issue for a 100K design.
There is one issue with SDF annotation. If you change your testbench and
restart your simulation, with the restart command the SDF annotation is
repeated even if the design is unchanged.
This is the same as for a VHDL-only simulation.
- Svein Haustveit
Nera Networks Bergen, Norway
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From: Gregg Lahti <gregg.d.lahti@intel.com>
John -
MTI makes a darn good simulator for cosim. It's the only single-kernel
simulator on the market. Having both languages running and debuggable
in the same simulator is the only way to go. I've use it here at Intel
in these dual-language configs with very good success:
- nothing but VHDL
- VHDL and Verilog RTL, VHDL test bench
- Verilog gate-level netlist, VHDL test bench
- nothing but Verilog
The latest relese 5.3c has some serious significant speed improvements
to Verilog. You'll note that Verilog has at least a 2-10X sim speed
improvement over VHDL simulation speed using modelsim for both languages,
depending upon how the VHDL & Verilog is written.
As far as caveats go, I can think of one where std_ulogic doesn't connect
up well with Verilog in co-sim; you need std_logic instead. ('Course, I
can think of a lot of reasons why one should use std_logic over
std_ulogic). It would be nice if modelsim could use the modelsim.ini file
to point to a Verilog library (not a sub-unit) instead of using the -L
[libname] from the command line. Haven't tried this method in the latest
5.3x variation, or it may be that modelsim just won't support it.
One of the nicest features of modelsim (Verilog or VHDL) is the TCL
interface. As an example, we were designing a custom micro-controller in
the middle of our ASIC and one of the engineers coded up a debugger window
in TCL/TK that connected into the uC during simulation. The debugger
showed all of the uC registers, program counter, and had the ability to
breakpoint the simulator on specific values in any register. Development
was a few days and about a few hundred lines of TCL/TK code. Very sweet,
saved man-weeks of effort debugging compiled assembly code from our SW team
on the RTL simulation. To do it in C/PLI/FLI would have been a serious
effort (especially the X windowing gunk), but the TCL/TK method in modelsim
was a slam-dunk.
- Gregg Lahti
Intel Corp Chandler, AZ
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From: [ I Wear My Sunglasses At Night ]
John, please keep me anon.
Couldn't wait to tell you how happy I'm with ModelSim. Of course, I've been
using it for years. However, I have also use VCS for years, happy with it
too.
However, we have most if not all of our models in VHDL and ALL of our test
benches in VHDL. I have been pushing Verilog since I've been here, and it
is starting to catch on. My last two project have run all the RTL sims in
VHDL and the gate sims in VHDL TB with Verilog gates. This runs seamlessly.
It speeds up the sim 10X faster than Vital.
Our current project we decided to go Verilog RTL and VHDL test bench and
models. Once again for legacy reasons. We made this decision after running
some tests. We converted a large block (about 30K gates) from VHDL to
Verilog RTL. About 3000 lines of code. The VHDL runs at about 4000 cyc/sec
the Verilog with the VHDL TB runs at 16K cyc/sec.
The other reason to use ModelSim is you don't have to recompile, or have
multiple binaries for each type of workstation. We currently have access
to HP's, Sun's, IBM's, and Linux. We can run sim's on which ever is
available or the fastest hardware at the time. BTW, Linux is at least
clock for clock as fast as HP and Sun (forget IBM) on X86. That means that
an 800MHz PIII is about 2x faster than a SUN Ultra 80 450MHz.
Now for the negative. ModelSim does not appear to be optimized for PLI's.
I have a design that is all Verilog, including the testbench, which has
several PLI's. Here VCS is much faster than ModelSim by 4x to 10x.
BTW, all my numbers are for ModeSim 5.3c and VCS 5.1.
- [ I Wear My Sunglasses At Night ]
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From: Rick Munden <munden@acuson.com>
Hi, John,
I have been using ModelTech's VHDL/Verilog cosimulation capability for
about 2 years. I am not using in quite the way Georg Zehentner is
asking about. In my environment ASICs and FPGAs are designed in Verilog
but off-the-shelf components are modeled in VHDL (see the Free Model
Foundry at http://vhdl.org/fmf). The board level design is netlisted in
VHDL. The testbench may be in either language but is most often in
Verilog. So far, ModelSim has done great. The only problem I am aware
of is an inability to have a Verilog tran primitive in a mixed language
simulation. Since these do not appear in RTL code it has not been an
issue. MTI performance is much better than our previous Verilog simulator.
- Rick Munden
Acuson
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From: "William E Lenihan III" <wlenihan@notes.west.raytheon.com>
Hi, John,
My case isn't exactly what Georg is looking for, but for what it's worth:
I've used ModelSim PE Plus 5.3a on a ~25k gate design that was 90% Verilog
and 10% VHDL for the UUT, with all Verilog for the testbench. I was very
impressed at how seamless the mix of the two languages went. I have no
quantitative info to support this, but compile times & simulation times
didn't seem to be any different from other, similarly-sized, single-language
designs/blocks I've worked on (but remember, it was a small design and only
a small fraction VHDL). Although written in synthesizable-RTL style code,
this model was never synthesized, so I can't comment on back-annotated sims.
In the writing of the code, there seemed to be only 2 caveats that had to be
followed:
1) When passing parameters in the parent Verilog module down to generics
in the child VHDL module, you could not use the 'defparam' construct,
but had to use the module instance parameter value list, ordered the
same way as the generics appear in the entity:
// vhdl component instantiated within Verilog ... ok for ModelSim:
cdecode #(2,4) U1 (.EN(1'b1), .AD(addr[1:0]), .DCODE(wordce[3:0]));
// vhdl component instantiated within Verilog ... NOT ok for ModelSim:
cdecode U1 (.EN(1'b1), .AD(addr[1:0]), .DCODE(wordce[3:0]));
defparam U1.s_addr = 2;
defparam U1.s_decode = 4;
2) There's another rule involving case sensitivity, but I lucked out in
that my default coding style never led to any problems.
It's all well documented in the ModelSim manuals. I couldn't be happier
with this simulator (well, actually, I could... if Model Tech would be
upfront about what parts of the LRM they don't support!)
- Bill Lenihan
Raytheon Systems Co. (formerly Hughes Aircraft Co.)
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