( SNUG 03 Item 9 ) ----------------------------------------------- [05/14/03]
Subject: Design Compiler, Cadence Get2chip, Ambit, Synplicity ASIC, Incentia
THE RICH GET RICHER: Last year, Synopsys owned the ASIC synthesis market.
This year, Synopsys now owns even more (if that's possible) of the ASIC
synthesis market:
Dataquest FY 2000 ASIC Synthesis Market Share
Synopsys ############################################ 87%
Cadence/Ambit ##### 10%
others ## 3%
Dataquest FY 2001 ASIC Synthesis Market Share
Synopsys ############################################## 91%
Cadence/Ambit ### 7%
Get2chips # 1%
others # 1%
One of the many jokes in this niche is that Cadence just bought Get2chips
for $90 million a few weeks ago. A couple of years back Cadence bought
Ambit for $260 million and it was as if they flushed this money down the
toilet. Cadence only got 10% at most of the ASIC synthesis market and that
was only by giving Ambit Buildgates away in package deals. That is, Cadence
has made only $26 million total off of Ambit since they bought Ambit; that's
a $234 million loss. ("Please put the seat down after flushing, OK?") Is
that extra $90 million for Get2chips going to be added to their $234 million
loss? You tell me after reading what the users said below.
The other noteworthy joke here is 4 weeks before DAC, Magma "suddenly"
announced they have "ended ASIC synthesis as we know it". Yawn. Two years
ago when Magma first came out they said they had ASIC synthesis then, too.
The only problem is that no one has ever used it! See ESNUG 374 #7.
The last two jokes are Synplicity ASIC and Incentia. Again, these two
suffer from an acute lack of paying ASIC synthesis customers. D'oh!
On the technical side of this survey, it appears that most Synopsys users
either haven't used DC's Automatic Chip Synthesis (ACS) feature or they
pretty much dislike it because it's too simple for their tastes. Also note
that the "free" DesignWare Foundation part of DC is welcome, but the "you've
gotta pay to use that bigger DW part" isn't loved by most users.
On the business side, under the PhysOpt part of this report you'll see that
(at a minimum) 77% of PhysOpt users must also use DC at part of their runs.
This means that DC won't be going away any time soon.
"Synopsys, Synopsys, Synopsys. Would love to see some stronger
competition, but hope that other users are the ones to take the
risk. (Yes, I know that's a paradox.)"
- Brian Schaufenbuel of LSI Logic
"In our flow we use Design Compiler plus ACS. Works fine. DesignWare?
Yes, there is a broad range on IP offered, from very (too?) simple to
very complex. The standard/simple models are incorporated in the
synthesis flows quite well, so you are not really affected by
DesignWare. For the complex models you need additional licenses, and
that is often too costly or expensive to negotiate."
- Markus Schutti of Infineon
"No idea on the synthesizers other than DC. DesignWare is OK at best
for simple things like counters but I've designed my own adder and
multiplier to better match my design requirements. We don't pay for
DC-Ultra so we can't use the better DesignWare objects. It's always
about money with Synopsys."
- Lance Flake of Maxtor
"Ambit requires 10 lines of code for running versus DC which requires
pages. Ambit has a fresher engine and easier to use for a beginner.
But DC is getting stronger with better usage and easier scripts. Have
not touched the others."
- Bengt-Erik Embretsen of Zarlink Semiconductor
"Ambit? There is still Ambit out there? (blink blink) Seriously, DC
is the tool of choice and they own the market. Automation is useless in
cutting edge/custom or semi-custom chip design. Same with synthesis
really. Good for ASICs and FPGAs and parts of the bigger designs these
days, but you cannot get top speed and smallest area from automated
synthesis flows in a semi-custom chip design any more. All synthesis
tools remain really outragously expensive, too."
- [ An Anon Engineer ]
"Synopsys vs Ambit? Pick one, stick with it. We were using DC. Our
big problem was verification. We needed to solve that one first,
before worrying about which synthesis tool did slightly better on which
examples. I haven't used ACS, but would like to give it a try. We've
used the basic DesignWare libraries, nothing fancy. Those work fine."
- Tom Thatcher, ex-Agilent and looking
"If history repeats itself (e.g. Silicon Perspective), Cadence will
stick it to the current users of Get2chips by putting their bloatware
around Get2chips, causing people to lose interest and seek the
functionality from other players without the extra $$ overhead.
Maybe Cadence can retain the IP and build on it rather than letting
it go old and stale like Ambit.
Anyway, we still use DC."
- Gregg Lahti of Microchip
"I wonder if Cadence's purchase of Get2chip isn't a good thing for
Synopsys, given that I had heard that Get2chip had won some low end
accounts away from Synopsys due to cost and given Cadence's track
record with its acquisitions."
- Martin Gravenstein of Time Domain Corp.
"DC clearly has the market mind share. Ambit was of interest when it
was independent, but it died when it became Cadence. I, unfortunately,
expect the same for Get2Chip. It definitely had some potential to at
least rattle Synopsys, and force the next jump in DC, the same as
happened because of Ambit. Both Ambit and Get2Chip are now where all
good tools go to die.
ACS is probably good for occasional users of DC, with low end chips,
but our chips don't qualify. We have our own make environment. We
generally only use the basic and foundation DW libraries, and both are
superior to what's offered by the competition, and built in data path
synthesis is not necessarily a replacement for a good DW library."
- [ An Anon Engineer ]
"Always used Synopsys Design Compiler. Tried other tools, always came
back to DC. May try Synopsys PhysOpt soon.
We have built so much capability on top of Design Compiler, that we
synthesize the 11 million gate device overnight (8-12 hours depending
on the network traffic) using an LSF compute farm, using about 12
machines in parallel. This capability includes lots of automatic
partitioning, selective top-down, bottom-up, side-to-side, etc,
automatic specing of clocks, timing, timing allocations, etc. We
looked at ACS two years ago when our capability was about 1/2 what
it is now, and would not have stepped down to what ACS had. The
concept of ACS is great, when filled out with all that we have."
- Bob Lawrence of Agere Systems
"We use DC, and haven't looked at the competition. We didn't need ACS.
The free DesignWare may have helped a bit, but also provided a little
bit of confusion looking at netlists. (What the heck is that? Oh,
yeah, that came from DesignWare.) The existence of both free and pay
libraries with the same basic name has certainly caused confusion here.
(We need xxx? Oh, I think that's available in DesignWare. Great, so
we can get it free? No, I don't think it's in the free DesignWare.
Then what does it cost?)"
- [ An Anon Engineer ]
"I liked Get2Chip's technology when we evaulated them a while back. I
hope Cadence doesn't mess this one up -- it would be a shame for the
Get2Chip team to break up and lose what they've developed so far. I'm
really tired of the capacity issues we have with Synopsys (when timing
gets tough, DC takes hours on a 100 k gate block -- and that's a small
block these days).
But we haven't put our money where my mouth is yet -- we're still
a DC house."
- Kris Monsen of Mobilygen
"I use Get2chips but not Synopsys DC. I'm not to be able to compare.
My experience with Get2chip is not very great. It seems to be lacking
a lot of simple features, like it cannot generate a wire load model.
Get2chips also has trouble making it formally clean in some designs."
- Srinivas Jammula of Procket Networks
"I've heard Cadence Ambit BuildGates is on par with Design Compiler.
It just has a different set of idosyncracies. No direct experience
however. DesignWare Foundation is too expensive. We use it, but in
a limited way."
- Tomoo Taguchi of Hewlett-Packard
"Interestingly enough we saw very little interface with Get2Chip. In
other words, we've done about 100 evaluations and we've only run into
Get2Chip that I know about in 3 cases. So it looks as if they have
really looked more at their COT market whereas we've been looking more
at the hand-off market. But we really hardly ever run into them. And
I do have to say in the 3 cases where the customer looked at Get2Chip
and us, Get2Chip didn't take any of those away from us. So I think it
is a good product, but I'm not sure how much a better product it is
than Ambit, so we will just have to see."
- Bernard Aronson, CEO of Synplicity, in his Q1 2003 call
"Is anyone actually using Synplicity ASIC? I haven't heard much noise
about it. I attended a joint Verplex/Synplicity ASIC seminar last
Fall, and Synplicity ASIC didn't impress me too much. I must say, it
does have some respectable benefits. Based on its similarities to and
synergy with Synpilify, it can find a niche in FPGA-to-ASIC conversions
and for FPGA engineers working on ASICs. However, DC and Ambit are the
real players."
- Saeed Coates of Paradigm Works, Inc.
"Entrusting Synplicity to synthesize your ASIC is like having McDonald's
cater your daughter's wedding. You may think you'll get the job done
for less money, but you'll pay for it in the long run."
- John Cooley, EE Times 3/11/02
"Have not used Ambit in 4 years. Got to silicon with it. I use DC.
I try to code my own simple logic add/sub/incr and see DW as a crutch.
But like DW for large blocks like UARTs. Haven't used ACS."
- Ross Swanson of Flextronics
"DC is first option, but too expensive. Ambit will be my choice.
DesignWare is quite good."
- Tie Li of Applause Technolgy
"We use Ambit. It's worked fine. The only problem is that the scripts
are different, and so many tools want constraints in DC format. Ambit
does have the ability to write DC scripts, but they're not perfect and
so the conversion process is kind of a pain. The good thing is that
Ambit includes all the DFT analysis and scan insertion that is not
supported in the base-version of DC. You get a LOT of bang for the
buck. These days that's a significant benefit given tight finances."
- David Frazer of Match Lab, Inc.
"Monday March 17
Session 1 - 9:00-10:30 - Synthesis Highlights in Design Compiler 2003
Fast talking lady going through busy slides about release DC 2003.06.
Her first statement was speed-ups in the new version of Synopsys.
Unfortunately her example wasn't very fortunate. 1M gates went from
30 to 8 hours when they optimized the scripts. Our chip takes only
2 hours to synthesize. I'm wondering what are we doing wrong... :)
A few new "features":
* Support of certain Verilog 2000 features. e.g., generate
* new variable to preserve sequential elements (two different
variables, on for elaboration and another for compilation)
* 2x faster than 2002.05. They claim it's because new algorithms
* Enhancements for data path synthesis
* Several enhancements to multiplier synthesis, mapping, ILM blocks,
constants optimization, boundary optimization, blah, blah, blah
* ACS (Automatic Chip Synthesis). This looks like an interesting
feature. They claim it takes the design, budgets it, and generate
synthesis jobs for the chip. If this is true, it could be the
solution to generate modular synthesis scripts/constraints
* Interface to Milkyway
* They claim that using group/ungroup require additional
operations in Formality
Q. I don't understand why Formality would fail when doing
group/ungroup
A. We want to preserve the names of the flops.
(note: After discussing the topic with real engineers, not Synopsys's,
the conclusion was that they want to preserve the name for flops so
they can do a name-only match in Formality.)"
- Santiago Fernandez-Gomez of Pixim, Inc.
"Everybody can get a free copy of Ambit Buildgates from Cadence.
I don't surprise at all that Cadence buys Get2chip.
I am testing the AMBA VIP from Synopsys. The documentation is
horrible. I have to go through the sales to get support. They need
to do a better job to support these VIP library."
- [ An Anon Engineer ]
"I only have experience with Synopsys Design Compiler, and none of the
other tools.
I don't use Automated Chip Synthesis (ACS). We have developed our own
scripting environment in our team and work with that. Our main focus
now is developing a hierarchical design flow for 90 nm. Block
synthesis/placement/clocktree using PhysOpt and SOC Encounter/NanoRoute
at the top-level."
- Alan Duffy of Motorola
"Tried ACS, didn't find anything great in it. The tool can't seem to
distinguish RAM's sizes from gates sizes which is a bummer for modules
that have RAM's. We are switching to Get2Chips for our synthesis flow.
The results are much better than Synopsys. Synopsys burnt us quite
badly with the ESNUG 403 #1 bug and took a ridiculous amount of time
to agree to the fact that it was a bug before fixing it.
DC_Shell is just a big mess where Synpopsys keeps patching new code
into. With every new patch they throw in a couple of new flags. Any
time you report a problem their support keeps jerking you around by
making you do different runs with different flag settings."
- [ An Anon Engineer ]
"A killer app would be the only thing that could de-throne Design
Compiler. Maybe a single house solution for RTL-to-GDSII like Monterey
has using Synplicity, but that's a long shot.
I love the ACS feature, it saves me tons of time, and I plan to use it
for all my designs."
- Patrick Allen of Infiniswitch
"ACS == crap. It's a waste of $$. Any designer worth his/her salary
could get similar results with GRID or LSF, or simple Perl scripting.
The 'top-down' design constraint stuff is dubious given that we don't
really trust our wireload models, so the whole value of ACS boils down
to a job distribution tool. Given that way it was presented at a
recent Synopsys road show, I'm betting ACS has very few users.
I still trust DC. Ambit is OK from what I've seen, but we have too
much invested in DC to change. Not tried Get2chips, Synplicity ASIC
or Incentia.
DesignWare is not really helpful for us other than adders, multipliers,
etc. The cost is too high for 'modules', and we can't readily prove
that these modules meet our needs."
- [ An Anon Engineer ]
"Synopsys has continued to make incremental improvements in synthesis.
There's been little incentive here to evaluate alternatives to DC."
- Matthew Henry of Agere Systems
"Haven't used any of the other synthesis tools, but I think Synopsys has
this going for them that their tool works well. Haven't used ACS.
Since we typically do a bottom-up design, I do not think ACS has any
use. The DesignWare stuff we use is more under the hood than directly.
So don't have much to say about it."
- [ An Anon Engineer ]
"We're still using PhysOpt and are still happy with it. We barely ever
use Design Compiler anymore. Usually just for linking or JTAG speed
type blocks. We do use some DesignWare blocks and are happy with their
performance."
- Chris Gorzek of Cray, Inc.
"I am not too much in favour of DesignWare. It's a good idea, but
doesn't serve the purpose. Their SocDBIST IP we got had some
optimization to be done anyway for which we needed to work on it
after DesignWare generated it."
- Amit Sanghani of Nvidia
"DC works. Don't fix what ain't broke."
- [ An Anon Engineer ]
"We use DC and we are pretty happy with it. Don't have any complaints
about what we use from DesignWare libraries."
- Amar Guettaf of Broadcom
"I use DC and Ambit Buildgates. I think DC is better in terms of run
time and results. Ambit works too hard while optimization for timing
constraints."
- [ An Anon Engineer ]
"Synopsys DC or DC-Ultra plus DesignWare has the same performance
(even poor) than Cadence's. Synopsys's are much more expensive, but
we do not plan to change synthesis tool."
- Rex Tung of InProComm
"We use Synopsys Design Compiler for ASIC, Synplicity for FPGA, VCS for
simulation, and Verplex for equivalency checks. I believe they give
the best performance/cost ratio for their applications."
- James Wang of Xiran
"Design Compiler:
My opinion of Design Compiler is dropping rapidly. Too many bugs. The
only experience I have with a different synthesis tool is IBM's
Booledozer a few years ago. There were occasional bugs there also, but
I don't think as many. This disadvantage was that we didn't find those
Booledozer synthesis bugs until we had chips back in the lab. Some of
the Design Compiler bugs are a bit easier to find. Like just try
reading in the netlist and you'll find out that DC didn't even generate
legal Verilog! Arghhhhh.
What I do like about Design Compiler is that it's constantly improving.
The Presto HDL reader generally gives better area, timing, and runtime
that the previous reader. Compile_ultra does generally give better
timing and area results than ordinary compiles.
DesignWare:
On a recent design, I needed a simple serial interface to be used for
loading a bunch of configuration registers. I got talked into using
JTAG because "it's easy, it's a standard, we can just use the TAP from
DesignWare, etc." What a pain in the ASCII. Our design needed to be
portable between many ASIC vendors. But, the DesignWare TAP included
asynchronous resets, which not all vendors appreciate. Also it had a
bunch of clock gating that I didn't like. And in synthesis, I ended up
with some buffers on the clock path even though I did all the
appropriate create_clock and dont_touch_network stuff. I would have
been better off designing my own serial interface. I may still look at
DesignWare if I need something in the future, but my first experience
was not so good."
- Matt Weber of Silicon Logic
"DC vs Ambit. I liked Ambit when they first started. I used it in 97,
and I loved their tcl interface and flexibility. Since then, Synopsys
learned the lesson and moved into tcl. We use DC now.
Now I don't know much about Ambit. I don't think it's any different
from DC.
DesignWare? -> don't like it. They charge you for not-much-better
gates (sometime worse, as we can see in our last chip where DesignWare
was generating slower logic than just some good Verilog coding).
In addition, I really hate all the overhead/headaches that DesignWare
introduces with non-standard naming (negative indexes!! and others),
problems w/ Formality (looks like now they are solved), non-convenient
synthesis (you can't avoid flattening of DesignWare... sigh.)"
- Santiago Fernandez-Gomez of Pixim, Inc.
"Based on my Verilog-synthesis training business, Synopsys is still the
overwhelming king of ASIC synthesis and Synplicity has emerged to take
a similarly dominant role in FPGA synthesis."
- Cliff Cummings of Sunburst Design
"We extensively use the Synopsys DC suite and have not found that we
need to consider others so far. The main issue in all design flows
is convergence from Design Compiler to SDF in the smoothest and
quickest possible way."
- Gregg Shimokura of STMicroelectronics
|
|
