"I am quite sure the powers that be at Cadence are not listening, so I'll
   be honest.  Clearly they don't see the need for courtesy in this area.
   When you commit your CEO to make a public appearance -- keynote, panel,
   you name it -- isn't there something in The Miss Manners Manual that
   says your guy should show up?  What am I missing here?  Maybe Fister's
   just a helluva lot busier than Aart, Wally, and Rajeev.  I'm not sure
   they'd buy into that reasoning, but who knows?  I don't.  Do you?"

       - Peggy Aycinena on the Cadence CEO Mike Fister skipping out
         on his DesignCon keynote, the DATE and DVcon CEO panels,
         and the John Sanguinetti Cancer Fundraiser.

( ESNUG 445 Subjects ) ------------------------------------------ [05/24/05]

 Item  1: Users Seek Demos and Dirt on Magma Cobra & Synopsys IC Compiler
 Item  2: After Seeing Online Demo, User Now Curious about TransEDA VN-Cover
 Item  3: ( DAC 04 #42 ) Three Users Chime in about Prolific ProTiming Tool
 Item  4: ( DAC 04 #24 ) A Boatload of Detailed FishTail User Benchmarks
 Item  5: ( ESNUG 443 #6 ) Users Note that DC XG Mode also Found in PhysOpt
 Item  6: ( ESNUG 443 #11 ) TetraMAX & FastScan Beat Cadence Encounter Test
 Item  7: ( ESNUG 435 #4 ) Aldec Active-HDL 6.3 Crushes Mentor ModelSim
 Item  8: ( ESNUG 443 #3 ) Erik's Follow Up to his Original Jasper Review
 Item  9: Mentor FPGA Laughs that Synplicity is Playing Catch-Up To Mentor
 Item 10: ( ESNUG 402 #2 ) Ex-Silicon Ensemble User Happy with PhysOpt/Astro
 Item 11: ( SNUG 04 #14 ) User Eval of PT-SI vs. CeltIC for Glitch Analysis
 Item 12: Magma Mojave Quartz DRC Pummels Calibre in User Benchmark (I)
 Item 13: Magma Mojave Quartz DRC Pummels Calibre in User Benchmark (II)
 Item 14: Magma Mojave Quartz DRC Pummels Calibre in User Benchmark (III)


============================================================================
 Trying to figure out a Synopsys bug?  Want to hear how 21,788 other users
    dealt with it?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
     !!!     "It's not a BUG,               
    /o o\  /  it's a FEATURE!"                 (508) 429-4357
   (  >  )
    \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
    _] [_         Verilog, VHDL and numerous Design Methodologies.

    Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
  Legal Disclaimer: "As always, anything said here is only opinion."
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   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)